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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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Multipurpose Security Protocol Accelerator
Complex system-on-chip (SoC) requirements can include security at the MAC layer, VPN layer, and application layer. The SynopsysSecurity Protocol Accelerator (SPAcc) IP addresses these needs with support for the Wi-Fi, MACsec, IPsec, SSL/TLS/DTLS, and SRTP security standards. The SPAcc
IP offers high throughput with support for mixed packet size traffic and low latency to preserve quality of service in voice and video applications in single- and multi-core processor architectures. The product is a highly customer configurable enabling solution to be tuned for specific applications providing differentiation in the market.
The Synopsys SPAcc optionally includes the following cryptographic support:
• 3GPP/LTE/LTE-Advanced wireless security: ZUC, SNOW 3G and KASUMI algorithms
• Chinese security: SM3 and SM4 algorithms
• DPA/TA side channel countermeasures: for AES, SM4, DES/3DES algorithms
IP offers high throughput with support for mixed packet size traffic and low latency to preserve quality of service in voice and video applications in single- and multi-core processor architectures. The product is a highly customer configurable enabling solution to be tuned for specific applications providing differentiation in the market.
The Synopsys SPAcc optionally includes the following cryptographic support:
• 3GPP/LTE/LTE-Advanced wireless security: ZUC, SNOW 3G and KASUMI algorithms
• Chinese security: SM3 and SM4 algorithms
• DPA/TA side channel countermeasures: for AES, SM4, DES/3DES algorithms
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