ONFI IO 2.2 /5.0

The INNOSILICON IPTM Mixed-Signal ONFI PHYs provide Turnkey physical interface solutions for ICs requiring access to ONFI compatible NAND FLASH devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports all ONFI NAND FLASH components in the market. The PHY components contain NAND FLASH specialized functional and utility critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any NAND FLASH interface.
The INNO AXI interface ONFI Controller (hereinafter referred to as “Controller”) provides four AXI channels to connect to the INNO ONFI PHY, which is compliant with the specifications of DFI digital interface.
This Controller takes two-layer architecture which makes the interface flexible and easy to be converted to the desired multi-port bus format and timing sequence. One layer is the CPU bus core with an arbitration for a single or a multiport CPU bus; the other layer is the controller core to communicate with the DFI PHY. Between the two layers, a generic command FIFO, TX/RX data FIFO is utilized to make the internal controller immune to the changes of the CPU bus core.
The overall design of the Controller is versatile, light-weight and easily adjustable to the CPU bus ports. It has high efficiency yet not overly large gate counts.
All interface timing on DFI and controller is in 1x SDR clock domain which can be half of the speed of the PHY core. The interface is fairly generic and supports high-performance input and output data flow, reaching to 4800Mbps ONFI speed in a wide range.

• see the entire ONFI IO 2.2 /5.0 datasheet
• get in contact with ONFI IO 2.2 /5.0 Supplier