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180nm MTP Non Volatile Memory for Standard CMOS Logic Process
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PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
The whole spectrum of PCIe 2.0 Base applications is offered by PCIe 2.0 transceiver IP. It adheres to the PIPE 3.0 standard. The PCIe 2.0 data rate at 5Gbps is supported by this IP, which incorporates high-speed mixed signal circuits. It also supports PCIe 1.0 data rate at 2.5Gbps. It is designed to consume less power and have a small die area. The needs for various channel conditions may be met by the PCIe 2.0 IP thanks to its support for both TX and RX equalization methods.
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Block Diagram of the PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
