PCIe 4.0 Serdes PHY IP, Silicon Proven in UMC 28HPC

With compliance for PIPE 4.4 interface spec, Peripheral Component Interconnect Express (PCIe) Gen4 PHY IP complies with PCIe 4.0 Base Specification. Capability for additional PLL control, reference clock control, and inbuilt power gating control leads to reduced power usage. Additionally, because the previously mentioned low power mode setting is programmable, the PHY is broadly suitable for a wide range of scenarios with diverse power consumption constraints.

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