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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
M31 PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 5.0 IP supports a complete range of PCIe 5.0 Base applications and is compliant with the PIPE 5.2 specification. The IP integrates high-speed mixed signal circuits to support 32Gbps PCIe 5.0 traffic and is backward compatible with 16 Gbps PCIe 4.0, 8.0Gbps PCIe 3.1, 5.0Gbps PCIe 2.1 and 2.5Gbps PCIe 1.1 data rates. With the support of TX and RX equalization techniques, the PCIe 5.0 IP is designed to meet the requirements of different channel conditions.
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Block Diagram of the PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
PCIe 5.0 IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N4P, N3E, N3P)