English
You are here:
PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270)
The VT18PLL500 is a macro cell for clock generation.
The output frequency is adjustable from 50 to 500MHz.
It is a fully integrated PLL based clock generator with a phase frequency detector (PFD), a low pass filter (LPF), a voltage controlled oscillator (VCO), and supporting circuitry such as fully programmable dividers. It is used for multiplication of stable clock source such as crystal oscillators.
Layout structure uses 1P4M (1poly and 4metal layers)
Layout does not use any special mask layer. (MIM or deep-Nwell layers are not required).
The output frequency is adjustable from 50 to 500MHz.
It is a fully integrated PLL based clock generator with a phase frequency detector (PFD), a low pass filter (LPF), a voltage controlled oscillator (VCO), and supporting circuitry such as fully programmable dividers. It is used for multiplication of stable clock source such as crystal oscillators.
Layout structure uses 1P4M (1poly and 4metal layers)
Layout does not use any special mask layer. (MIM or deep-Nwell layers are not required).
View PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270) full description to...
- see the entire PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270) datasheet
- get in contact with PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270) Supplier
PLL IP
- TSMC CLN7FF 7nm Clock Generator PLL - 800MHz-4000MHz
- TSMC GF Intel Samsung Deskew Frequency Synthesizer PLL
- TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL
- TSMC GF Intel Samsung Integer-N Frequency Synthesizer PLL
- Jitter Cleaner PLL Digital Loop Filter
- TSMC Intel 32kHz Low-bandwidth Frequency Synthesizer PLL