MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Power-On-Reset IP
It generates POR_OUT signal to reset the digital logic. The POR signal is set low if analog supply or digital supply falls below the threshold voltage, and will be set high if both of analog supply and digital supply exceed the threshold voltage.
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