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NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm)
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Programmable Interrupt Controller
This interrupt controller can be used to bundle several different interrupt sources into one main system interrupt.
The interrupt controller provides an enable register for each source request. The interrupt status register displays the current pending interrupts, the masked status register shows the status of all enabled interrupt sources. Each pending interrupt can be acknowledged individually without affecting any other interrupts. This features helps to avoid situations where a new interrupt happens while the CPU is in the middle of the interrupt service routine.
The interrupt controller provides an enable register for each source request. The interrupt status register displays the current pending interrupts, the masked status register shows the status of all enabled interrupt sources. Each pending interrupt can be acknowledged individually without affecting any other interrupts. This features helps to avoid situations where a new interrupt happens while the CPU is in the middle of the interrupt service routine.
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Block Diagram of the Programmable Interrupt Controller IP Core
