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Run Time Phase Alignment Circuit
This is a All Digital Phase Alignemnt Circuit. It uses Approximate local clock and incoming data and generates a Phase Aligned and Frequency Aligned Clock at the receiver end. This Generated Clock at the receiver end is avaliable within one clock duration.
This generated clock is aligend to the transmitter clock. it is generated at the receiver side by receiver clock and receiver data.
Receiver clock can be of +/- 5% of clock frequency of the transmitted clock and phase shift between clocks is not atall a issue.
This IP can operate at giga Hz ranges and can facilitate to transfer long packets without need of any phase or clock extraction and alignment circuitry.
This generated clock is aligend to the transmitter clock. it is generated at the receiver side by receiver clock and receiver data.
Receiver clock can be of +/- 5% of clock frequency of the transmitted clock and phase shift between clocks is not atall a issue.
This IP can operate at giga Hz ranges and can facilitate to transfer long packets without need of any phase or clock extraction and alignment circuitry.
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