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SATA 3.0 Host Controller
The SATA-HC IP block simplifies the integration of high capacity SSDs utilizing SATA I/II/III at 1.5/3/6Gbit/s data rates using Xilinx FPGAs.
Combined low-latency and high throughput is achieved by accessing the SSD directly from FPGA logic with no external circuitry. The lower protocol layers Phy/Link/Transport are implemented in an all-RTL solution, which minimizes access time by providing the shortest possible path between SSD and application.
Combined low-latency and high throughput is achieved by accessing the SSD directly from FPGA logic with no external circuitry. The lower protocol layers Phy/Link/Transport are implemented in an all-RTL solution, which minimizes access time by providing the shortest possible path between SSD and application.
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Block Diagram of the SATA 3.0 Host Controller IP Core
