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USB-C 3.1 SS/SSP PHY in Type-C in TSMC (16nm, 12nm, N7, N6, N5, N5A)
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Scalable Cache Coherency
Scalable cache coherency solution for many-core architecture:
* up to 1024 fully coherent cores.
* optimized protocol with false sharing prevention
* configurable for heterogeneous multi-cores with distributed L2 and adaptive L3 caches.
* up to 1024 fully coherent cores.
* optimized protocol with false sharing prevention
* configurable for heterogeneous multi-cores with distributed L2 and adaptive L3 caches.
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Block Diagram of the Scalable Cache Coherency IP Core
