English
You are here:
Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
View Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers full description to...
- see the entire Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers datasheet
- get in contact with Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers Supplier
Block Diagram of the Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
AXI4-Stream Interface IP
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- DMA AXI4-Stream Interface to AXI Memory Map Address Space
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- Receives video data from Flir's Lepton IR-sensors, Video over SPI (VoSPI)
- DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
- DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List