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Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
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Block Diagram of the Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
AXI4-Stream Interface IP
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