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Serial FPDP
Serial Front Panel Data Port is an industry standard, low-overhead, low-latency, high speed serial communications protocol. sFPDP is ideal for use in applications such as high-speed communication system backplanes, high-bandwidth remote sensor systems, signal processing, data recording, and high-bandwidth video systems. The simple and lightweight nature of the protocol makes it an attractive choice for replacement of parallel bus interconnects using serial transceiver technology. sFPDP can be used in point-topoint or loop topologies, uni-directional or bidirectional links, and easily supports different types of data with efficient and flexible data framing options.
StreamDSP is committed to performance, efficiency, and flexibility. Our sFPDP core is unique in that we support nearly all transceiver based devices from Altera and Xilinx. We’re always making improvements to the core with innovative new features such as multi-lane bonding for increased bandwidth, and we’re continually updating the core to support new transceiver based devices offered by both Altera and Xilinx. Our core provides a open interface to the FPGA transceiver, giving the user complete control over transceiver speed, settings and adjustments. A complete reference design is provided for each family, as well as a thorough testbench with support for Aldec's Active- HDL and Riviera-Pro as well as Mentor's ModelSim tools. In addition, our testing procedure includes exhaustive Altera <-> Xilinx interoperability testing to ensure compatibility.
StreamDSP is committed to delivering the highest level of customer support to ensure a smooth system integration. We also offer IP core customization and FPGA design services.
StreamDSP is committed to performance, efficiency, and flexibility. Our sFPDP core is unique in that we support nearly all transceiver based devices from Altera and Xilinx. We’re always making improvements to the core with innovative new features such as multi-lane bonding for increased bandwidth, and we’re continually updating the core to support new transceiver based devices offered by both Altera and Xilinx. Our core provides a open interface to the FPGA transceiver, giving the user complete control over transceiver speed, settings and adjustments. A complete reference design is provided for each family, as well as a thorough testbench with support for Aldec's Active- HDL and Riviera-Pro as well as Mentor's ModelSim tools. In addition, our testing procedure includes exhaustive Altera <-> Xilinx interoperability testing to ensure compatibility.
StreamDSP is committed to delivering the highest level of customer support to ensure a smooth system integration. We also offer IP core customization and FPGA design services.
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Block Diagram of the Serial FPDP IP Core
