Serial protocol Interface Slave

The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master. The MSPIS IP can be programmed to run either in standard SPI mode where bidirectional one byte transactions are implemented, or in extended SPI mode where frame transactions are implemented through 14-bits address and 16 or 32-bits data. The MSPIS IP controls all SPI-bus specific sequences, protocol and timing. This IP can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.

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