LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
Single precision, IEEE 754, floating point to integer conversion
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IEEE 754 IP
- Single precision, IEEE 754, floating point adder
- Single precision, IEEE 754, floating point multiplier
- IEEE 754 Floating Point Coprocessor
- Single precision floating-point fast speed parametrized multi operands adder
- Single precision floating-point 2 cycle's multiplier
- Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs