SMIC 65nm LL SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application

Features

• SSTL_18/ SSTL_2/ LPDDR/ LVTTL COMBO interface for DRAM application;
• SMIC 65nm Logic Low Leakage 1P10M Salicide 1.2V/1.8V/2.5V Process;
• Cell Size (Width * height) (35~80)um * 211um with DUP stagger bonding pads;
• Work voltage: 1.8V/2.5V/3.3V;
• Programmable driven-strength, programmable ODT, optional pullup,pulldown resistor; support data rate up to 800Mbps;
• Suitable for 7, 8, 9 and 10 layers application ;