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Tessent UltraSight-V
Tessent UltraSight-V, part of the Tessent Embedded Analytics product family, is a comprehensive solution for RISC-V based SoCs. With a combination of embedded IP and software, UltraSight-V empowers embedded software engineers in developing high-performance embedded software. Utilizing effective, non-intrusive techniques and processor trace based on the Efficient Trace (E-trace) standard, this solution minimizes debugging delays and accelerates your SoC projects, ensuring they meet their market deadlines.
Tessent UltraSight-V includes a set of IP modules that provide extensive visibility into how the software behaves in the system. The Processor Analytic (PAM) IP module provides run control capabilities. Utilizing the Direct Memory Access (DMA) IP module, code can be uploaded to the SoC 70-100X faster than using normal GDB load. Leveraging the Static Instrumentation IP module, printf-style debugging with timestamps can be done with 20X fewer instructions. The virtual console module provides a bidirectional communication channel between software running on the target and the debug host. It replaces conventional UART based communication with no need for an additional physical port. All IP modules are run-time programmable.
Tessent UltraSight-V’s Enhanced Trace Encoder (ETE) provides a mechanism to monitor the program execution of a CPU in real time. It encodes instruction execution and, optionally, data memory accesses, and outputs data in a highly compressed format. The device execution can be fully reconstructed off-line. Siemens is a key contributor to the RISC-V Efficient Trace (E-Trace) standard and the Enhanced Trace Encoder supports all the mandatory and optional capabilities in the E-Trace specification. It also provides cycle-accurate trace, which simplifies software performance optimization.
Tessent UltraSight-V includes the flexible Host Suite software environment, enabling command-line, scripted, and IDE-based debug and interaction with the IP modules.
Tessent UltraSight-V includes a set of IP modules that provide extensive visibility into how the software behaves in the system. The Processor Analytic (PAM) IP module provides run control capabilities. Utilizing the Direct Memory Access (DMA) IP module, code can be uploaded to the SoC 70-100X faster than using normal GDB load. Leveraging the Static Instrumentation IP module, printf-style debugging with timestamps can be done with 20X fewer instructions. The virtual console module provides a bidirectional communication channel between software running on the target and the debug host. It replaces conventional UART based communication with no need for an additional physical port. All IP modules are run-time programmable.
Tessent UltraSight-V’s Enhanced Trace Encoder (ETE) provides a mechanism to monitor the program execution of a CPU in real time. It encodes instruction execution and, optionally, data memory accesses, and outputs data in a highly compressed format. The device execution can be fully reconstructed off-line. Siemens is a key contributor to the RISC-V Efficient Trace (E-Trace) standard and the Enhanced Trace Encoder supports all the mandatory and optional capabilities in the E-Trace specification. It also provides cycle-accurate trace, which simplifies software performance optimization.
Tessent UltraSight-V includes the flexible Host Suite software environment, enabling command-line, scripted, and IDE-based debug and interaction with the IP modules.
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Block Diagram of the Tessent UltraSight-V IP Core
RISC-V IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- 32-bit Embedded RISC-V Functional Safety Processor
- 64-bit RISC-V Application Processor Core
- Dual-issue Linux-capable RISC-V core