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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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TSMC CL013G 130nm Clock Generator PLL - 68MHz-340MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock input, a 1-4096 divider in the internal feedback path, and a 1-8 divider at the output. The outputs are 50% duty cycle for all output divider values.
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