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Wi-Fi 6 (ax)+BLEv5.4+15.4 Dual Band RF IP for High-End Applications.
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TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock input, a 1-4096 divider in the internal feedback path, and a 1-8 divider at the output. The outputs are 50% duty cycle for all output divider values.
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