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TSMC CLN5FF GLink 2.3LL Die-to-Die PHY
IGAD2DY04A is a high-speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL interconnect and Chip-on-Wafer-on-Substrate (CoWoS®) with silicon interposer. IGAD2DY04A contains 56 TX lanes and 56 RX lanes per slice and supports 8 slices in one PHY. Each TX/RX lane can support up to 17.2 Gbps data rate. In summary, IGAD2DY04A offers a full-duplex data transmission with extremely low power and up to 963.2 Gbps data rate per slice in both directions.
Each TX/RX slice contains PMA and PCS modules. PMA supports serialization, de-serialization, data transmission, eye training, and lane repair functions. PCS provides data bus inversion (DBI), CRC check, and FIFO functions. One PLL is also included in IGAD2DY04A to generate an 8.5 GHz high-speed clock for data transmission.
IGAD2DY04A is designed and fabricated in TSMC 5 nm FF CMOS process with 1.2 V analog supply voltage for PLL/PMA and 0.75 V analog/digital supply voltages. Independent low power mode for PLL and slices is available.
Each TX/RX slice contains PMA and PCS modules. PMA supports serialization, de-serialization, data transmission, eye training, and lane repair functions. PCS provides data bus inversion (DBI), CRC check, and FIFO functions. One PLL is also included in IGAD2DY04A to generate an 8.5 GHz high-speed clock for data transmission.
IGAD2DY04A is designed and fabricated in TSMC 5 nm FF CMOS process with 1.2 V analog supply voltage for PLL/PMA and 0.75 V analog/digital supply voltages. Independent low power mode for PLL and slices is available.
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