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TSMC CLN6FF Asynchronous Read Two Port Register File Compiler
IGMDLRX01A is an asynchronous read and synchronous write ULVT periphery two port register file compiler (2PRF). It is developed with TSMC 6nm 0.75V/1.8V CMOS LOGIC FinFET Process. Different combinations of words, bits, and column-selected number (MUX) could be used to generate the most desirable configurations.
Given the desired size and timing constraints, the IGMDLRX01A compiler is capable of providing suitable asynchronous 2PRF instances models within minutes. It is capable of automatically generating the data sheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length could be neglected as long as the setup/hold times and minimum high/low pulse widths requirements are satisfied. This allows a more flexible clock falling edge during each operation.
Given the desired size and timing constraints, the IGMDLRX01A compiler is capable of providing suitable asynchronous 2PRF instances models within minutes. It is capable of automatically generating the data sheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length could be neglected as long as the setup/hold times and minimum high/low pulse widths requirements are satisfied. This allows a more flexible clock falling edge during each operation.
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