UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
BlueLynx™ interconnect IP subsystem includes physical (PHY) and optional link layer for chiplet interfaces and supports Universal Chiplet Interconnect Express (UCIe), OpenCompute Project (OCP) Bunch of Wires (BoW), as well as custom applications.
The BlueLynx™ link layers connect to on-die buses/Networks-on-Chip (NoCs) with various standards, including AXI4, AXI5 lite, CHI, ACE, and more.
Customers receive industry-standard ASIC integration views with reference silicon bring up platform and software required for first-pass silicon success in the shortest amount of time. Die-to-Die subsystem solutions have been delivered in over 7 different process nodes to date across multiple semiconductor foundries.
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