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Ultra-Compact Data Encryption Standard (DES/3DES) Core
The DES1 ASIC/FPGA core is an implementation of the DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard. It processes 64-bit blocks, with one, two, or three 56-bit keys.
Basic core is very small (3,000 ASIC gates). Enhanced versions are available that support
various cipher modes (ECB, CBC, OFB, CFB,
CTR).
The design is fully synchronous and available in both source and netlist form. Test bench
includes the NIST DES test vectors.
DES Core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.
Basic core is very small (3,000 ASIC gates). Enhanced versions are available that support
various cipher modes (ECB, CBC, OFB, CFB,
CTR).
The design is fully synchronous and available in both source and netlist form. Test bench
includes the NIST DES test vectors.
DES Core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.
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Block Diagram of the Ultra-Compact Data Encryption Standard (DES/3DES) Core
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