NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm)
UMC L130HS 130nm DDR DLL - 104MHz-520MHz
TCI can configure this block to have almost any number of slaves (which delay the arbitrary signals) with a single master section (which establishes the time base) to minimize area and power. The slave delays can be independently set to precise values or dynamically adjusted after determining the boundaries of a data eye. The DDR DLL has excellent linearity and very high resolution.
TCI can also configure this block to output multi-phase clocks directly from the reference clock.
View UMC L130HS 130nm DDR DLL - 104MHz-520MHz full description to...
- see the entire UMC L130HS 130nm DDR DLL - 104MHz-520MHz datasheet
- get in contact with UMC L130HS 130nm DDR DLL - 104MHz-520MHz Supplier