130GF_LVDS_01 is a LVDS receiver with data rate up to 400 Mbps (DDR mode). The LVDS receiver converts input LVDS signal to differential CMOS 1.5V standard and transmits it through the OUTP and OUTN outputs. The input signal can be supplied with or without AC decoupling. If the signal is supplied to the receiver input without AC decoupling, then it must have an external VCM. Otherwise, the internal VCM is used. The IP block can be used as a clock receiver with frequency up to 1.2 GHz. The LVDS has a terminating resistor with an adjustable value. The internal reference current can be adjusted to optimize the power consumption of the LVDS receiver.