NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm)
USB 2.0 Device Controller IP
Optionally, the controller can be provided with no DMA Engine and no buffering, operating in a cut-through mode forwarding and receiving USB payloads and managing only the USB protocol. In this case, the customer can implement their own differentiated DMA engine.
Optionally, a simple transmit and receive buffer is included in this configuration which can be accessed by software over the slave register access interface (typically AHB). This option results in very low-footprint hardware, useful for scenarios where the software can completely manage USB traffic including sequencing of the USB transactions.
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Block Diagram of the USB 2.0 Device Controller IP IP Core
USB IP IP
- HDCP 2.3 Embedded Security Modules on DisplayPort/USB Type-C
- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
- USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
- Multi-protocol SerDes PMA
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core