TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries, multiple metalstacks
USB 2.0 Serial Interface Engine with UTMI
The USB 2.0 Controller implements a full USB 2.0 interface at a rate of 480Mbits/s and 12Mbits/s. Separate interrupts for each endpoint and reset simplifies software implementation. The endpoints have a capacity of up to 64 Bytes in bulk mode ensuring an optimum transfer rate.
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Block Diagram of the USB 2.0 Serial Interface Engine with UTMI
USB2.0 Serial Interface Engine UTMI IP
- USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
- USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
- USB 3.0 PHY IP, Silicon Proven in UMC 40SP
- USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC