USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+

The Combo PHY is a complete USB 3.0 and PCIe 2.0 PHY IP solution designed for a mobile and data consumer applications in TSMC 28nm process. It supports both USB3.0 (1 or 2 ports) and PCIe 2.0 (1 lane). It consists of Physical Coding Sublayer and Physical Media Attachment and includes all circuitry for interface operation with 8/10 encoding/decoding, driver, input buffers, PLL and impedance matching circuitry. The PHY provides standard PIPE interface with the Media Access Layer for exchanging information. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.

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