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USB2.0 Host Transceiver PHY
USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) and Low-Speed Transceivers and is compliant with the USB 2.0 Specification and latest Revision of the On the Go and UTMI+ Specifications. It includes Clock/Data Recovery, on-chip PLL, Integrated & Calibrated Termination and Pull-Up/Down Resistors with full Analog Transceiver functionality for the Complete USB 2.0 PHY as illustrated in the figure. USB2 HOST transceiver has standard UTMI with SIE so that ASIC vendors are isolated from the high speed and analog circuitry associated with the transceiver, thus reducing the design risk and fastening the design cycle.
The core’s main blocks are clock/data recovery for FS/HS, PLL, transceiver state machines, data encoder/decoder and high-speed analog transceiver as can be seen in the main block diagram above.
The core’s main blocks are clock/data recovery for FS/HS, PLL, transceiver state machines, data encoder/decoder and high-speed analog transceiver as can be seen in the main block diagram above.
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Block Diagram of the USB2.0 Host Transceiver PHY IP Core
