USB2.0 OTG PHY supporting UTMI+ level 3 interface - 40LL / 110G / 130G / 130EF

The OTG PHY supports up to UTMI+ level 3. The area and power is pretty minimal compared with other vendors. In order to minimize the power and area, innovative architecture and techniques are used in the design. In order to make the integration and mass production easy, many BIST features are included digital loop back only, mixed signal loop back which enables loopback from the PAD. This greatly helps the chip testing in mass production stage. Currently, 0.13um/0.11um design has been fully verified. 65nm/55nm design has been ready for tape out. 40nm design will also be ready very soon.

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