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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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USB2.0 PHY - SMIC 180nm Logic
Features
- Low cost;
- Low EMI; Low size: 0.29mm2
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USB2.0 PHY IP
- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
- USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
- USB2.0 Host Transceiver PHY
- USB2.0 OTG PHY supporting UTMI+ level 3 interface - 40LL / 110G / 130G / 130EF
- USB2.0 OTG PHY supporting UTMI+ level 3 interface - 28HK/55LL
- USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP