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Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
The BitCsi2Rx IP is a receiver for camera sensor signals, to be used in an FPGA or ASIC.
It receives camera signals in accordance with the MIPI CSI-2 and D-PHY specifications. BitCsi2Rx converts these signals to parallel video signals for AXI4- Stream Video standard. To make it easier to interface BitCsi2Rx with various other design blocks, it also outputs fval (frame valid) and lval (line valid) signals for synchronization.
Third generation of the IP, so it very compact, from only 500 LUTs/FFs, including the D-PHY.
A MIPI CSI-2 transmitter IP is also available from BitSim, BitCsi2Tx.
It has been used with SoCs like: i.MX8-series (NXP), OMAP (TI), MPSoC (Xilinx), Snapdragon (Qualcomm) and Xavier (Nvidia).
It receives camera signals in accordance with the MIPI CSI-2 and D-PHY specifications. BitCsi2Rx converts these signals to parallel video signals for AXI4- Stream Video standard. To make it easier to interface BitCsi2Rx with various other design blocks, it also outputs fval (frame valid) and lval (line valid) signals for synchronization.
Third generation of the IP, so it very compact, from only 500 LUTs/FFs, including the D-PHY.
A MIPI CSI-2 transmitter IP is also available from BitSim, BitCsi2Tx.
It has been used with SoCs like: i.MX8-series (NXP), OMAP (TI), MPSoC (Xilinx), Snapdragon (Qualcomm) and Xavier (Nvidia).
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Block Diagram of the Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
