VESA DSC (Display Stream Compression) 1.2b Video Encoder
Features
- VESA DSC 1.2b compliant
- Supports all DSC 1.2b mandatory encoding mechanisms
- MMAP, BP, MPP, and ICH
- Output buffering compatible with transport stream over video interfaces
- Configurable maximum display resolution
- Up to 4K (4096x2160), 5K (UHD+), and 8K (FUHD)
- 8, 10, 12, 14, and 16 bits per video component
- YCbCr and RGB video input format
- 4:4:4, 4:2:2, and 4:2:0 native coding
- 1 pixel / clock internal processing architecture in 4:4:4
- 2 pixels / clock internal processing architecture in 4:2:2 and 4:2:0
- Parameterizable number of parallel slice encoder instances
- (1, 2, or 4) to adapt to the capability of the technology and target display resolutions used
- Multiple slices per line in each encoder instance supported
- 100% verification coverage based on UVM environment
- Verified against the VESA DSC 1.2b C model using a comprehensive test image library
- Backward compatible with DSC 1.1
View VESA DSC (Display Stream Compression) 1.2b Video Encoder full description to...
- see the entire VESA DSC (Display Stream Compression) 1.2b Video Encoder datasheet
- get in contact with VESA DSC (Display Stream Compression) 1.2b Video Encoder Supplier
Block Diagram of the VESA DSC (Display Stream Compression) 1.2b Video Encoder
VESA DSC Video Encoder IP
- VESA DSC (Display Stream Compression) 1.2b Video Decoder
- ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
- VESA DSC 1.2b Encoder for Xilinx FPGAs
- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- VESA DSC Encoder and Decoder IP Solutions
- VESA DSC V1.2 Encoder