400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Video Design Framework for Multi-camera Vision Applications
Instead of starting from scratch and having to spend months designing and building a new design framework, users of the logiREF-ACAP-VDF design framework can immediately focus on specific vision-based parts of their next ACAP design. This design implements six parallel video inputs from Xylon video cameras and the display output with RGB overlay. All video inputs are stored in the video memory, and by mean of on-board push buttons, the user can select each of them for the single camera or all cameras full screen display output.
All logicBRICKS IP cores are supplied with bare-metal and appropriate Linux software drivers. The provided video capture and display demo applications run in Linux OS.
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