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FPGA / CPLD News

• Xilinx Doubles Industry's Highest Capacity Device to 4.4M Logic Cells, Delivering Density Advantage that is a Full Generation Ahead (Tuesday Dec. 10, 2013)
  Xilinx today announced a new record breaking 4.4M logic cell device, more than doubling its industry leading highest capacity Virtex®-7 2000T device, achieving two consecutive generations of high-end leadership, and delivering an extra node worth of customer value.
  
  
• Xilinx 20nm All Programmable UltraScale Portfolio Now Available with ASIC-class Architecture and ASIC-strength Design Solution (Tuesday Dec. 10, 2013)
  Xilinx today announced availability of its 20nm All Programmable UltraScale™ portfolio with product documentation and Vivado® Design Suite support. Xilinx shipped its first 20nm silicon in early November 2013, continuing to execute on an aggressive UltraScale device rollout. These devices deliver an ASIC-class advantage with the industry's only ASIC-class programmable architecture coupled with the Vivado ASIC-strength design suite and UltraFast™ design methodology.
  
  
• Altera Enables Immediate 20 nm Design Starts with Quartus II Software Arria 10 Edition (Monday Dec. 02, 2013)
  Altera today released the Quartus® II software Arria 10 edition, the industry’s first development tool support for 20 nm FPGAs and SoCs. Based on TSMC 20 nm process technology, Arria® 10 FPGAs and SoCs effectively reinvent the midrange FPGA and SoC category by simultaneously delivering a 15 percent performance gain over current high-end FPGAs and up to 40 percent lower power than previous midrange devices
  
  
• Xilinx's Comprehensive Functional Safety Design Package Enables Smarter Factories and Medical Equipment (Tuesday Nov. 26, 2013)
  Xilinx today announced its comprehensive functional safety design package for industrial, automotive, medical, aerospace and defense applications according to IEC 61508 and ISO 26262 safety standards.
  
  
• Altera Demonstrates Integrated PLC and HMI System on a Single Chip (Monday Nov. 25, 2013)
  Altera today announced a key development in automation system design at the SPS IPC Drives 2013 conference - implementation of a programmable logic controller (PLC) and human machine interface (HMI) system on a single chip.
  
  
• Xilinx Accelerates Machine Vision Application Design Productivity for Zynq-7000 All Programmable SoCs (Monday Nov. 25, 2013)
  Xilinx today announced accelerated design productivity for machine vision applications, leveraging HALCON and VisualApplets development platforms to create an end-to-end Smarter Vision development environment for the Zynq®-7000 All Programmable SoC.
  
  
• Microsemi Announces PCI Express 2.0 SIG Certification for the Industry's Lowest Power SmartFusion2 SoC FPGAs and IGLOO2 FPGAs (Wednesday Nov. 20, 2013)
  Microsemi today announced that its SmartFusion®2 SoC FPGAs and IGLOO®2 FPGAs have achieved PCI® Express (PCIe) 2.0 endpoint specification certification
  
  
• Lattice Semiconductor and Helion Demonstrate New FPGA-Based Machine Vision Camera Solutions (Tuesday Nov. 19, 2013)
  Lattice and Helion GmbH today announced they will demonstrate several new FPGA-based camera design solutions at next week's SPS IPC Drives exhibition in Nuremberg, Germany.
  
  
• Altera Brings FPGA-based Acceleration to IBM Power Systems and Announces Support for OpenPOWER Consortium (Monday Nov. 18, 2013)
  Customers are now able to develop OpenCL code that targets IBM Power Systems CPUs and accelerator boards with Altera FPGAs as a high-performance compute solution.
  
  
• Microsemi Releases Industry-leading EnforcIT Security Monitor; Advanced Security IP for Its SmartFusion2 SoC FPGAs and IGLOO2 FPGAs (Friday Nov. 15, 2013)
  Microsemi announced it has released EnforcIT® Security Monitor, an advanced security IP block providing additional layers of user-configurable tamper protection and responses to the most secure and lowest power FPGA product families on the market—Microsemi's SmartFusion®2 SoC FPGAs and IGLOO®2 FPGAs.
  
  
• Altera Accelerates Performance of Suricata Network Security Monitoring Engine with Stratix V FPGAs and OpenCL (Friday Nov. 15, 2013)
  Altera today announced the first successful demonstration of the Suricata Engine, an open-source Network Intrusion Detection and Prevention (IDS/IPS) system.
  
  
• Xilinx Ships Industry's First 20nm All Programmable Product (Monday Nov. 11, 2013)
  Xilinx today announced first customer shipment of the semiconductor industry's first 20nm product manufactured by TSMC, and the PLD industry's first 20nm All Programmable device.
  
  
• Altera Quartus II Software v13.1 Delivers Up to 70 Percent Reduction in Compile Times (Wednesday Nov. 06, 2013)
  Altera today announced the release of its Quartus® II software version 13.1, extending its industry leadership in software productivity by delivering on average 30 percent and up to 70 percent reduction in compile times compared to the previous version, through significant algorithm optimization and increased parallelization.
  
  
• Altera Announces Quad-Core 64-bit ARM Cortex-A53 for Stratix 10 SoCs (Tuesday Oct. 29, 2013)
  Altera today announced that its Stratix 10 SoC devices, manufactured on Intel’s 14 nm Tri-Gate process, will incorporate a high-performance, quad-core 64-bit ARM Cortex™-A53 processor system, complementing the device’s floating-point digital signal processing (DSP) blocks and high-performance FPGA fabric.
  
  
• Vivado Design Suite 2013.3 Accelerates Productivity with Design Methodology, Next Generation Plug-and-Play IP, and Partial Reconfiguration (Wednesday Oct. 23, 2013)
  Xilinx today released the Vivado Design Suite 2013.3, featuring support for the new UltraFast™ design methodology, enhanced configuration, integration and verification of Plug-and-Play IP, and Partial Reconfiguration.
  
  
• Xilinx Introduces UltraFast Design Methodology for Vivado Design Suite (Wednesday Oct. 23, 2013)
  Xilinx today introduces the UltraFast™ design methodology for Vivado® Design Suite, a comprehensive design methodology for enabling accelerated and predictable design cycles for design teams using the Vivado® Design Suite.
  
  
• Altera DC-DC Power Converter Solutions Improve System Power Efficiency by up to 35 Percent while Reducing Board Area by up to 50 Percent (Monday Oct. 21, 2013)
  Altera today announced four new reference designs that leverage the power technology obtained through its acquisition of Enpirion®. The reference designs provide FPGA users and board developers turnkey power solutions that increase power efficiency by up to 35 percent, reduce board area by up to 50 percent, and reduce overall bill-of-material (BOM) bulk capacitance costs by up to 50 percent versus competing power solutions.
  
  
• Xilinx and TSMC Reach Volume Production on all 28nm CoWoS-based All Programmable 3D IC Families (Monday Oct. 21, 2013)
  Xilinx Inc. and TSMC today announced production release of the Virtex-7 HT family, the industry’s first heterogeneous 3D ICs in production.
  
  
• Altera SDK for OpenCL is First in Industry to Achieve Khronos Conformance for FPGAs (Wednesday Oct. 16, 2013)
  
  
  
• Altera Supports China Mobile Research Institute in Developing Next-Generation Wireless Networks (Monday Oct. 07, 2013)
  Altera today announced its collaboration with China Mobile Research Institute (CMRI) to research and develop next-generation wireless networks based on the Centralized Radio Access Network (C-RAN) architecture.
  
  
• Altera Begins Production Shipments of FPGA Industry's Highest Performance SoCs (Wednesday Sep. 25, 2013)
  Altera today announced production availability of its Cyclone® V SoCs and engineering sample availability of its Arria® V SoCs. With increased processor peak clock frequencies these devices are the FPGA industry’s highest performing SoCs.
  
  
• Lattice Announces MachXO3 FPGA Family; Most Advanced, Lowest Cost per I/O Programmable Bridging and I/O Expansion Solution (Tuesday Sep. 24, 2013)
  MachXO3 FPGA Family Brings 640 to 22K Logic Cells, Lowest Power, 1 Cent per I/O, and Hard IP Blocks to Ease Implementation of Emerging Connectivity Interfaces
  
  
• Xilinx and Analog Devices Achieve JEDEC JESD204B Interoperability (Tuesday Sep. 24, 2013)
  Xilinx and Analog Devices today announced that they have achieved JESD204B interoperability between Xilinx JESD204 LogiCORE™ IP in the Kintex®-7 FPGA and the ADI AD9250 analog-to-digital high-speed data converter.
  
  
• Xilinx Showcases Industry's First FPGA-based 80Gbps Network Interface Card (NIC) and New Intel QPI Interface Implementation at IDF13 (Wednesday Sep. 11, 2013)
  Based on Xilinx SmartCORE IP, 80Gbps Traffic Manager NIC and QPI interface solutions deliver significant performance gain and latency reduction
  
  
• Xilinx and its Ecosystem Expand All Programmable Abstractions to Empower More Designers and Accelerate Productivity up to 15X (Tuesday Sep. 10, 2013)
  Xilinx and its Ecosystem Expand All Programmable Abstractions to Empower More Designers and Accelerate Productivity up to 15X
  
  
• Altera Demonstrates Broadcast Solutions at IBC 2013 (Tuesday Sep. 10, 2013)
  Altera and Texas Instruments Showcase Industry’s First 12G Serial Digital Interface That Doubles Transmission Rates for 4K Video Broadcast Systems
  
  
• Altera and Micron Lead Industry with FPGA and Hybrid Memory Cube Interoperability (Wednesday Sep. 04, 2013)
  Altera and Micron today announced they have jointly demonstrated successful interoperability between Altera Stratix® V FPGAs and Micron’s Hybrid Memory Cube (HMC).
  
  
• Algo-Logic Systems launches Full Order-Book running on a single-FPGA Platform (Friday Aug. 30, 2013)
  Algo-Logic Systems today announced availability of their new Full Order-Book solution. The Full Order-Book performs all book building processing and reporting as logic inside a single FPGA. The Low Latency Order-Book is designed using the on-chip memory for customer book sizes with many thousands of open orders, a dozen symbols, and reporting of ten L-2 levels.
  
  
• Lattice Just Made It Easier for OEMs to Introduce the Latest in MIPI Camera and Display Capabilities (Wednesday Aug. 28, 2013)
  MIPI DSI and CSI Tx/Rx Reference Designs Help Designers Overcome the Challenges of Integrating Camera and Display Capabilities to Their Systems
  
  
• Altera Demonstrates Interlaken Connectivity with Cavium OCTEON Multicore Processors (Tuesday Jul. 30, 2013)
  Altera today announced the interoperability of its Interlaken intellectual property (IP) core on Stratix V FPGAs with Cavium's OCTEON multicore processors. This accomplishment simplifies an OEM's device decision-making process by ensuring chip-to-chip connectivity upfront.