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IP / SOC Products News

• Tiempo announces a fully-asynchronous delay insensitive DES crypto-processor chip (Wednesday Jun. 11, 2008)
  Tiempo released a clock-less crypto-processor chip - DES4- including four different DES cores available as IP and able to execute standard ciphering algorithms DES, DES-1, 3DES & 3DES-1.
  
  
• GDA Demonstrates its PCI-Express Gen 2 Controller (GPEX-GEN2) at 5Gbps for High Performance Applications (Wednesday Jun. 11, 2008)
  GDA Technologies today announced successful functional operation of its Gen2 PCI Express Controller on its hardware platform.
  
  
• Lattice Expands Wireless Solutions with 3GPP-LTE CTC Decoder IP Core (Monday Jun. 09, 2008)
  TurboConcept Optimizes its 3GPP-LTE Turbo Decoder IP Core for LatticeSC/M and LatticeECP2/M FPGA Devices
  
  
• IPextreme® Brings ColdFire® Architecture to the FPGA Masses (Monday Jun. 09, 2008)
  IPextreme today announced an FPGA-optimized soft version of Freescale’s V1 ColdFire® core available free of charge to Altera’s Cyclone III FPGA customers
  
  
• Freescale and Altera Partner to Deliver World's First Soft ColdFire(R) Cores on FPGAs (Monday Jun. 09, 2008)
  Popular V1 Core Available at No Charge Through IPextreme for Altera's Cyclone(R) III FPGA; SOPC Builder-Ready Component Backed by Broad Ecosystem
  
  
• Dolphin Integration launches their SESAME library for High Voltage and Low Leakage in 0.18 µm (Monday Jun. 09, 2008)
  Direct connection to the battery (e.g. Li-Ion) for some logic islets of SoCs requires dealing with “high voltage”, up to 3.6 V, while for others ultra low leakage is needed far below the performances offered by products available on the market.
  
  
• Noesis Technologies releases 10Gbps AWGN channel emulator IP (Friday Jun. 06, 2008)
  The core is fully programmable, able to support throughput rates up to 10Gbps, rendering it an ideal solution for channel emulation of high data rate applications such as GPON, G.975 and others.
  
  
• Innovaide Releases Licensable Packet Processing and Traffic Management IP (Thursday Jun. 05, 2008)
  Innovaide is First-to-Market with licensable Carrier Grade designs for Classification, Forwarding and Traffic Management. The Verilog blocks scale from 5Gig to 40Gig performance in FPGA/ASIC implementations.
  
  
• Arasan Chip Systems PCI Express Gen2 Solution Named to PCI-SIG Integrators List (Thursday Jun. 05, 2008)
  New Flexible PCIe IP Core and Development Platform Passes Rigorous Interoperability and Compliance Testing
  
  
• Evatronix enhances its Ethernet MAC product line with MAC-1G PCS IP core (Thursday Jun. 05, 2008)
  Physical Coding Sublayer (PCS) add-on to the successful MAC-1G controller provides new opportunities for an already wide range of possible implementations.
  
  
• Imagination Technologies Extends Low-Power Receiver IP Platform (Thursday Jun. 05, 2008)
  Imagination Technologies announced today that it has added NorDig-Unified 1.0.3.compliant DVB-T to its licensable receiver IP platform family.
  
  
• Virage Logic Supports TSMC's Power Trim Service(TM) for Advanced Process Nodes (Tuesday Jun. 03, 2008)
  With its advanced tradeoff capabilities, SiWare Memory users can achieve static power savings of up to 35 percent, 70 percent or 90 percent depending on their selection of the built-in light sleep, deep sleep and shut-down modes available in 40nm memories.
  
  
• Virage Logic Delivers Open RTL to Test Floor Embedded Memory Test and Repair Subsystem (Monday Jun. 02, 2008)
  New Release of STAR Memory System Expands Availability of Subsystem Beyond Virage Logic Memories to Third-Party and Internally Developed Memories
  
  
• ARM Mali-400 MP Technology Brings High-end Graphics to all Consumer Devices (Monday Jun. 02, 2008)
  ARM today announced the ARM® Mali™-400 MP scalable multiprocessor graphics solution, capable of delivering performance of up to 1G pixels per second and enabling licensees to serve multiple product markets with the same architecture, whilst retaining the flexibility to choose the optimum power, performance and area configuration for their application.
  
  
• Xilinx Meets Performance Requirements of LTE Wireless Systems With New LogiCORE Turbo Encoder and Decoder Solutions (Friday May. 30, 2008)
  The new Xilinx 3GPP LTE Turbo Encoder and Decoder LogiCORE(TM) offerings deliver throughput speeds of up to 200 Mbps with the embedded digital signal processing (DSP) capabilities of Spartan(R) and Virtex(R) field programmable gate arrays (FPGAs)
  
  
• Denali First to Release Full DDR3 DIMM IP Solution (Thursday May. 29, 2008)
  This new DDR3 DIMM offering adds unique capabilities in the memory controller and PHY IP that are needed for networking, storage and personal computing systems using DDR3 modules at data rates up to 12.8GBytes/s per DIMM.
  
  
• DapTechnology announces VHDL Testbench for its FireLink Extended 1394b link layer controller IP Core (Wednesday May. 28, 2008)
  The FireLink Extended Testbench is transaction based and allows verification level and diagnostic tests to be performed from a system level perspective.
  
  
• Virage Logic Speeds Time-to-Market with an All-Digital, High-Performance DDR2/3 PHY+DLL Solution (Wednesday May. 28, 2008)
  Supporting speeds of up to 1066 Mbps in 65-nanometer (nm) G processes, the all-digital Intelli DDR2/3 PHY+DLL achieves performance and resolution levels that were previously only possible with analog solutions.
  
  
• MIPS Technologies Unveils Silicon-Proven Hi-Fi Audio Playback IP With Lowest Power Consumption Available (Tuesday May. 20, 2008)
  The new Audio Codec IP achieves an impressive 100dB dynamic range and -93dB THD while consuming only 7.8mW power when playing back through stereo line outputs at 48kHz.
  
  
• Algotronix launches unique DesignTag system for detecting proprietary intellectual property within an operating chip (Monday May. 19, 2008)
  DesignTag consists of a small, low power, IP core which is added to the design to be protected and DesignTag reader software and data logging hardware which can sense the tag through the chip package. Each DesignTag IP core has a unique identification code which can be used to look up details of the protected product in a database.
  
  
• Evatronix announces its fifth 8051 ISA-based SoC Development Platform - HDLC Connectivity. (Monday May. 19, 2008)
  HDLC controller joins other IP cores in the R8051XC-based platform family, Ethernet MAC and USB Controllers, to shorten time-to-market for data communication solutions
  
  
• NEC develops Adobe Flash Lite IP (Monday May. 19, 2008)
  At Embedded Systems Expo here, NEC System Technology showed an evaluation board featuring what the company claims as the world's first intellectual property (IP) designed to play back content encoded in Adobe Flash Lite.
  
  
• Sidense SLP Memory IP Targets Low Power OTP Applications (Tuesday May. 13, 2008)
  Sidense today announced the Sidense Low Power (SLP) one-time programmable (OTP) memory macrocells for low-power and cost-sensitive applications that require highly secure information storage.
  
  
• Virage Logic Embedded Multi-Time Programmable Non-Volatile Memory Gains Acceptance in Military Applications (Tuesday May. 13, 2008)
  NOVeA(R) Memory Features 100K Cycle Programming Endurance, 125 Degrees Celsius Storage Temperature and Minimum of 10-Year Data Retention - Manufactured on a Standard CMOS Logic Process
  
  
• Faraday Announces Successful Implementation of 533 MHz ARM(R) Compliant Core -- FA626 in 130nm SoC ASIC (Tuesday May. 13, 2008)
  Faraday Technology today announced that it has successfully integrated a hardened 533Mhz ARM(R) compliant core -- FA626 in a complex 130nm SoC ASIC for Radioframe Networks.
  
  
• Cosmic Circuits Announces New IP-cores with "Ready for IBM Technology" Validations (Tuesday May. 13, 2008)
  Cosmic Circuits Receives IBM Advanced Business Partner Certification and Completes 90nm Silicon Validations in the Power-Management and A/D Converter Space
  
  
• TranSwitch announces Industry’s Most Flexible Programmable Silicon Platform for Access Applications (Monday May. 12, 2008)
  The first platform, Taurus, which is targeted for access applications, provides programmability, flexibility and cost effectiveness unsurpassed in the market. Taurus includes a targeted set of access interfaces, including GPON, Ethernet, and POTS/TDM.
  
  
• ARM Announces PrimeCell Generic Interrupt Controller (Monday May. 12, 2008)
  The Generic Interrupt Controller (GIC) is a high-performance, area–optimized PrimeCell peripheral supporting the ARM Generic Interrupt Controller architecture. Highly configurable and programmable, the GIC is suitable for single and multi-processor systems, presenting a common Programmer’s Model accessible via AMBA® 3 AXI™ or AMBA AHB-Lite™ interfaces.
  
  
• Dolphin Integration: A Commercial Breakthrough for 'Reduced Cell Stem Libraries' (Monday May. 12, 2008)
  Upon launching against all odds, the daring RCSL concept of "Reduced Cell Stem Libraries" for Standard Cells, through a partnership with the Swiss Research Center CSEM, a series of design wins at diverse Fabless customers have proven its worth under the brand name of SESAME.
  
  
• Allegro introduces world's first H.264/MPEG-4 AVC High-Profile/High-Definition Hardware Video Encoding IP (Tuesday May. 06, 2008)
  Allegro’s H.264 IP core is a real-time hardware encoder targeting mobile phones, camcorders, set-top boxes, webcams and video surveillance applications. Allegro’s IP core can process images up to high-definition resolutions.