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IP / SOC Products News

• videantis introduces new scalable video solutions up to HD for mobile devices (Wednesday Apr. 30, 2008)
  By combining powerful video engines with a programmable stream unit, the v-MP20x0MOB solution packages are capable of encoding and decoding video up to 720p resolution in a wide range of standards on extremely small silicon area without placing load on the host CPU.
  
  
• Arasan Chip Systems Announces PCI Express Gen2 End Point Solution (Tuesday Apr. 29, 2008)
  Arasan’s PCIe IP core is fully compliant with the PCI-SIG PCIe specification 2.0, increasing throughput to 5 GT/s, while maintaining backward compatibility with Gen 1 systems. Designed to the PIPE specification 1.87, it provides a reliable physical layer interface to industry standard PHYs.
  
  
• Altera and HCELL Engineering Announce DO-254-Certifiable Nios II Embedded Processor (Tuesday Apr. 29, 2008)
  The embedded processor core complies with the objectives and requirements of the DO-254 hardware avionic standard and meets the highest design-assurance levels. This safety-critical version of the Nios II processor is offered through HCELL Engineering to customers who must comply with DO-254 requirements.
  
  
• TranSwitch announces first HDMI 1.3 PHY IP Core operating at 10.5 Gbps (Tuesday Apr. 29, 2008)
  The HD-PXL-1.3 transmitter IP core is available in two versions. The first version meets all the current HD (High Definition) standards up to 2.25 Gbps. The second version supports serial communications at a speed of up to 3.5 Gbps per channel for extended HD resolutions, with backward compatibility to the first version of 2.25 Gbps.
  
  
• Synopsys Releases Silicon Proven 5.0 Gbps PCI Express 2.0 PHY IP (Monday Apr. 28, 2008)
  The DesignWare PHY IP for PCI Express 2.0 includes advanced built-in diagnostic capabilities and ATE test vectors enabling at-speed production testing of the PHY. It is implemented in standard CMOS digital technologies and does not require special process options, providing both ease of integration into a SoC, and ensuring high production yields.
  
  
• ASIC Architect Announces the Availability of DDR 3 Controller Cores (Monday Apr. 28, 2008)
  The DDR 3 Controller Core supports JEDEC’s DDR 3 DRAM architecture. The DDR 3 Controller core combined with the newly released Multi-Port Intelligent Arbiter and Scheduler (MPIAS) Core provides a winning solution for the high-end ASIC/SoC customers looking for high performance measured by low latency, low power, high throughput, QOS, and fairness control.
  
  
• ASIC Architect Announces the Availability of Multi-Port Intelligent Arbiter and Scheduler for DDR Controller Cores (Monday Apr. 28, 2008)
  ASIC Architect, Inc. today announced the availability of Multi-Port Intelligent Arbiter and Scheduler (MPIAS) with optional AMBA 3 AXI or AMBA 2 AHB Interface for it successful DDR Controller Cores.
  
  
• Dolphin Integration announces a SESAME Library stem for ultra low power and low voltage in 0.18 um (Monday Apr. 28, 2008)
  Dolphin Integration's low power and low voltage library SESAME uVSvHS enables operating as low as 0.9 V in 0.18 µm and is available in TSMC G, TSMC ULL and IBM process.
  
  
• ARC Introduces New "Sonic Focus-Ready" Audio/Video Subsystem (Thursday Apr. 24, 2008)
  The AM 401V offers a fully integrated yet programmable subsystem that is capable of playing back virtually any audio/video content on portable media devices. An industry first, it is optimized to popular audio formats such as AAC, MP3, Dolby Digital and video standards such as MPEG-4, Real Video, VC-1 and H.264 while greatly improving sound fidelity.
  
  
• Virage Logic's DDR Memory Controller Interface Provides High Performance Data Transfer at Higher Efficiency and Lower Power (Tuesday Apr. 22, 2008)
  Architected from the ground up to provide a combination of low-latency, high-performance and low-power options, the Intelli DDR solution incorporates intelligent scheduling algorithms for superior system bandwidth.
  
  
• Impinj Introduces Few-Time Programmable Logic Nonvolatile Memory Solution (Monday Apr. 21, 2008)
  Impinj today announced the introduction of the AEON®/FTP family of logic nonvolatile memory IP at Taiwan Semiconductor Manufacturing Corporation’s 130, 90, and 65 nm process nodes.
  
  
• CEVA Unveils High-Performance, Low Power Platforms for Wireless, Multimedia Applications (Monday Apr. 21, 2008)
  The platforms come in two versions, the CEVA XS-1100A optimized for wireless baseband applications, and the CEVA XS-1200A aimed at multimedia and other applications requiring high-performance signal processing.
  
  
• Northwest Logic Announces Availability Of A Complete PCI Express 2.0 Solution For Xilinx Virtex-5FXT Devices (Monday Apr. 21, 2008)
  This solution combines Northwest Logic’s full-featured PCI Express 2.0 Core, DMA Back-End Core, DMA Driver and PCI Express GUI to provide a complete, pre-packaged PCI Express 2.0 solution.
  
  
• Evatronix SDIO-HOST Controller compliments the company's line of memory controllers (Monday Apr. 21, 2008)
  The SDIO-HOST Controller is fully compatible with SD Memory version 2.00, SDIO version 2.00 and MMC version 3.31 protocols. The register set complies with SDIO Host Specification ver. 1.00 and supports an optional DMA controller as well.
  
  
• Kilopass Announces XPM Is First CMOS Logic NVM Technology to Complete Qualification on 80nm and 90nm Process Technologies (Thursday Apr. 17, 2008)
  Kilopass Technology today announced that its extra-permanent memory (XPM) technology is the first high density embedded NVM technology to complete qualification for 80nm and 90nm process technologies with the successful qualification of its XPM-80GC and XPM-90LP product families.
  
  
• Virage Logic Strengthens Low Power IP Product Portfolio with Availability of 65nm CPF-Enabled Ultra-Low-Power Standard Cell Libraries (Thursday Apr. 17, 2008)
  Virage Logic’s SiWare™ Logic Ultra Low-Power Standard Cell libraries now include CPF technology views that identify specialized cells available in the library to enable advanced power saving capabilities. Included are always-on cells, isolation cells, level shifter cells, power switch cells and state retention cells to support a full range of advanced low-power techniques
  
  
• Digital Core Design announces D6802 8-bit Microprocessor Core (Thursday Apr. 17, 2008)
  D6802 is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow. Customer can select VHDL, VERILOG HDL Source code, and FPGA Netlists depending on what is preferred.
  
  
• Start-up OptNgn Offers a Floating Point VHDL Library as Open Source (Wednesday Apr. 16, 2008)
  OptNgn today announced that it is offering a floating point VHDL library under the GPLv3 Open Source License. FPGA designers can now save months of coding and debug time by using these floating point libraries instead of creating the VHDL from scratch.
  
  
• GDA Announces the Availability of PCI Express Single Root IOV (GPEX-SRIOV) IP (Tuesday Apr. 15, 2008)
  GPEX-SRIOV IP is a flexible and configurable design targeted for end-point, root complex, switch and bridge implementation for both Gen1 and Gen2 applications.
  
  
• Synopsys Delivers Industry's First Certified USB 2.0 PHY IP for Advanced 45-Nanometer Process (Tuesday Apr. 15, 2008)
  Synopsys' industry-leading USB 2.0 nanoPHY mixed-signal IP, now available in the 45-nm process node, uses half the power and die area compared to previous USB PHY IP solutions and enables faster time-to-market with reduced risk.
  
  
• Silicon Image Delivers Advanced 12 Megapixel Camera Processor IP Core for Mobile Devices (Tuesday Apr. 15, 2008)
  This technology delivers professional picture quality and advanced camera functionality once only found in digital still cameras (DSCs), but now conveniently integrated into mobile phones, portable multimedia players (PMPs), ultra mobile PCs (UMPCs) and security cameras.
  
  
• Dolphin Integration announces an embedded high rejection LDO powering sensitive Analog Components (Tuesday Apr. 15, 2008)
  Dolphin Integration launches an Ultra-Low Drop-Out Regulator dedicated to the supply of sensitive analog blocks: LR-2.8~4.2/1.8~3.3.
  
  
• ARM Enhances Feature Set of Popular Cortex-M3 Processor for Extreme Low-Power Functionality (Monday Apr. 14, 2008)
  The latest release includes a new Wake-Up Interrupt (WIC) controller which allows almost instantaneous return to fully active mode from an Ultra-Low Leakage (ULL) retention state and introduces enhanced power management features that address the ongoing need in the embedded market for increased performance and longer battery life in next-generation designs.
  
  
• PLDA announces immediate availability of PCIe 2.0 IP Core supporting new Xilinx Virtex-5 FXT FPGAs (Thursday Apr. 10, 2008)
  PLDA, the industry leader in the high-speed bus IP market, today announced the immediate availability of their PCIe Gen 2 FPGA IP support for the Virtex®- 5 FXT platform.
  
  
• Imaging Solutions Group (ISG) announces High Speed FireWire(tm) IEEE-1394b Intellectual Property (Wednesday Apr. 09, 2008)
  ISG has implemented the 1394b Link Layer as an IP Core solution in Verilog and it can be ported to any FPGA or ASIC solution. Currently implemented in a Xilinx Spartan 3 FPGA for simplicity, low-cost, & space-efficiency it is fully compatible with IEEE-1394 IIDC DCAM specifications.
  
  
• Virage Logic First to Deliver Complete Memory Compiler and Logic Library IP Portfolio for TSMC 40nm Process (Monday Apr. 07, 2008)
  Virage Logic Corporation today announced the availability of memory compilers and logic libraries for TSMC’s 40-nanometer (nm) process.
  
  
• Wipro-NewLogic demonstrates IEEE 1394b Link IP Cores for PC, Consumer, Storage & Automotive applications (Monday Apr. 07, 2008)
  In one of the demonstrations for 1394b OHCI Link, Wipro showcased data transfer between an external Hard Disk Drive and a PC along with simultaneous streaming of video from the external hard disk. The PC was connected to Wipro’s PCI based platform running the IEEE 1394b OHCI IP core along with Window’s IEEE 1394 drivers and a 3rd party PHY.
  
  
• Dolphin Integration announces an ultra High Density library in shrunk processes. (Monday Apr. 07, 2008)
  Dolphin Integration's standard cell library SESAME uHDvLC is already known for its cost reduction capability in the standard processes 0.18 and 0.13 µm. Its ultra High Density enables silicon costs reduction and its very Low Power offers the possibility to reduce packaging costs.
  
  
• Novelics Announces Availability of Single-Transistor SRAM for 65-nanometer System-On-Chip Desgin (Thursday Apr. 03, 2008)
  coolSRAM-1T™Is Only 65nm SRAM-1T Available in Standard Bulk CMOS process for High-Density Embedded Memory Applications
  
  
• Synopsys' New DesignWare IP Significantly Simplifies Transition to PCI Express (Wednesday Apr. 02, 2008)
  The DesignWare LE IP for PCIe is a cost-effective solution that provides ease-of- use features to simplify the complexities of transitioning to PCI Express for applications requiring a single lane, such as existing PCI/PCI-X designs, ExpressCards, Ethernet controllers, SATA controllers and wireless hubs.