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Ultra-low power 32 kHz RC oscillator designed in GlobalFoundries 22FDX
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SpringSoft and Magma Validate Full Interoperability of Custom Chip Design Tools with TSMC 65nm iPDK (Tuesday Dec. 01, 2009)
SpringSoft and Magma® Design Automation have completed cross-tool validation using TSMC's 65nm interoperable process design kit (iPDK).
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DOLPHIN Integration promotes Application Hardware Modeling to optimize system functions (Monday Nov. 23, 2009)
DOLPHIN Integration promotes a novel approach to the development of Virtual Components of Silicon IP, namely “Application Hardware Modeling”. AHM aims at optimizing any critical function performed jointly by parts of the system, comprising some Virtual Component within a SoC, its PCB with relevant discrete components, such as Quartz, PMIC, or MEMS, along with application software.
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Calypto Empowers Intrinsity to Deliver Industry's Fastest, Most Power-efficient Third-party Processor Cores (Monday Nov. 23, 2009)
Calypto today announced that Intrinsity is deploying Calypto’s SLEC® RTL tool for the comprehensive verification of its products. Intrinsity implements industry‐standard, cycle‐accurate RTL cores from ARM®, PowerPC® and MIPS® in its Fast14® one‐of‐N domino logic to increase performance by as much as 65 percent, while maintaining low leakage and operating power characteristics in approximately the same silicon area.
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Magma's Quartz DRC and Quartz LVS Adopted by Toshiba Corporation for Verification and Yield Improvement of Advanced Flash Memory Designs (Monday Nov. 23, 2009)
Toshiba standardized on Magma's physical verification products after validating their accuracy on 32-nanometer (nm) designs. Quartz DRC's and Quartz LVS's advanced features were shown to improve the yield and reliability of Toshiba's flash memory designs.
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Klocwork Launches New Family of Developer Productivity Tools (Thursday Nov. 19, 2009)
Klocwork today announced Klocwork Insight Pro a new suite of developer tools aimed at maintaining high velocity throughout the software development process.
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AppliedMicro Chooses Carbon Model Studio for System-Level Modeling, Validation (Tuesday Nov. 17, 2009)
Carbon Design Systems™ announced today that AppliedMicro has selected Carbon’s system-level model generation software to reduce time to market for its next-generation system on chip (SoC) designs.
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Paradigm Works Releases RegWorks Spec2Reg as Free, Open Source Software (Tuesday Nov. 17, 2009)
Paradigm Works today announced that it has released its RegWorks™ Spec2Reg tool as Free Open Source Software (FOSS) for the chip development community.
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Atrenta's SpyGlass-CDC Solution Boosts IP Integration Efficiency for Fujitsu Kyushu Network Technologies (Tuesday Nov. 17, 2009)
Atrenta today announced that Fujitsu Kyushu Network Technologies, has adopted its SpyGlass®-CDC product. Fujitsu Kyushu Network Technologies will broadly deploy the tool to help reduce design risks associated with semiconductor IP integration.
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eASIC Introduces eTools 8.0 (Monday Nov. 16, 2009)
eASIC today announced the immediate availability of its eTools 8.0 software suite for implementing 45nm Nextreme-2 designs.
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Magma Announces BoardView: Extends Chip-Based Navigation to Circuit- and Board-Level Debug -- Traces Signals Between Chips, PCBs or MCMs, Speeding Board-Level Failure Analysis (Monday Nov. 16, 2009)
Magma(R) Design Automation today announced BoardView(TM), a new software that extends CAD navigation and circuit debug from integrated circuits (ICs) to printed circuit boards (PCBs) and multichip modules (MCMs).
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Mentor Graphics Outlines Strategy to Unify Silicon Test and Yield Analysis (Monday Nov. 02, 2009)
Mentor today outlined its strategy and roadmap to help customers address the growing test challenges they face in moving to smaller process nodes and more complex, low-power, mixed-signal systems-on-chip (SOCs). As part of this strategy, Mentor is uniting its award-winning embedded compression and automatic test pattern generation (ATPG) technology with the leading built-in self-test (BIST) technology from recently acquired LogicVision into a new product line, called Tessent™.
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Freescale and Synopsys Announce Multi-year Strategic Collaboration Agreement to Increase Verification Productivity (Monday Oct. 26, 2009)
Synopsys today announced the expansion of its verification collaboration with Freescale.
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Magma RTL-to-GDSII Implementation Selected by Mellanox Technologies for 40-nm Multimillion-gate Communications ICs (Monday Oct. 26, 2009)
Magma today announced that Mellanox Technologies, a leading supplier of end-to-end connectivity solutions for servers and storage that optimize data center performance, has selected the Talus 1.1 RTL-to-GDSII implementation system to be included in its 40-nanometer (nm) IC design flow.
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Synopsys Enables Optimized High-Performance Energy-Efficient ARM Processor-based Designs (Tuesday Oct. 20, 2009)
Synopsys today announced that it has created an optimized reference implementation methodology for the ARM® Cortex™-A8 processor that achieves greater than 2GHz (4000 DMIPS) at 540mW.
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Cadence and ARM Fabric Collaborate to Increase Engineer Productivity and Drive Down Time to Market for SoC Integration (Monday Oct. 19, 2009)
Cadence and ARM today announced that the two companies have entered into a strategic collaboration to create a next-generation SoC design flow that will accelerate time to market and lower the cost of SoC integration and verification.
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SMIC Adopts Cadence DFM Solutions for 65- and 45-Nanometer IP/Library Development and Full Chip Production (Monday Oct. 19, 2009)
Cadence today announced that SMIC has adopted Cadence(R) Litho Physical Analyzer and Cadence Litho Electrical Analyzer to more accurately predict the impact of stress and lithographic variability on the performance of 65- and 45-nanometer semiconductor designs
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Intune Networks selects Duolog’s Bitwise register management tool (Monday Oct. 19, 2009)
Duolog today announced that Intune Networks has chosen Duolog's Bitwise tool to manage the register and memory-map infrastructures of Intune’s next generation telecommunications networking products.
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Synopsys Introduces Synphony High Level Synthesis (Monday Oct. 12, 2009)
Synopsys today introduced its Synphony HLS (High Level Synthesis) solution that integrates M-language and model-based synthesis to deliver up to 10X higher design and verification productivity than traditional RTL flows for communications and multimedia applications.
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Open Virtual Platforms (OVP) Initiative for Multi-Core Software Development Releases High Performance Models of ARM Processors (Thursday Oct. 08, 2009)
The Open Virtual Platforms (OVP) initiative has released new models of ARM processor cores. These models work with the OVP simulator, OVPsim, and have exceptionally fast performance of hundreds of millions of instructions per second (MIPS).
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Cadence Extends Its TLM-Driven Design and Verification Solution to Support Leading Embedded Software Environments (Tuesday Oct. 06, 2009)
The Cadence® Incisive® Enterprise Simulator (IES) and Incisive Software Extensions (ISX) TLM verification solutions now support Open Verification Methodology (OVM)-based TLM hardware/software co-verification, unified TLM and C/C++ hardware/software co-debugging, plus embedded software symbolic debug support for C/C++ compilers from ARM, GNU, Green Hills Software and ARC (now part of Virage Logic).
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Cadence Introduces Incisive Enterprise Verifier, Delivering Dual Power of Formal Analysis and Simulation Engines (Monday Oct. 05, 2009)
New Integrated Solution Increases Return on Investment from Assertion-Based Verification and Eases Adoption for Design and Verification Engineers
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ChipStart Offers a Subsystem Alternative for SoC System Management (Thursday Oct. 01, 2009)
ChipStart announced today the availability of a new SoC intellectual property hardware and software combination, called SSM, which consolidates power, security, error recovery, and boot management by using an SoC subsystem approach.
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IMEC sets major step towards 3D integration of DRAM on logic (Thursday Oct. 01, 2009)
IMEC and its 3D integration partners have taped-out Etna, a new 3D chip integrating a commercial DRAM chip on top of a logic IC. The new 3D stack resembles as close as possible to future commercial chips. It consists of a 25µm thick logic die on top of which a commercial DRAM is stacked using through-silicon vias (TSVs) and micro-bumps. IMEC and its 3D integration partners have taped-out Etna, a new 3D chip integrating a commercial DRAM chip on top of a logic IC. The new 3D stack resembles as close as possible to future commercial chips. It consists of a 25µm thick logic die on top of which a commercial DRAM is stacked using through-silicon vias (TSVs) and micro-bumps.
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Dolphin Integration announces the availability of assessment result of its High Density stem for benchmarking purposes (Monday Sep. 28, 2009)
Dolphin Integration is announcing the availability of the first assessment results on this Motu Uta logic standard: diverse users indeed are in a position to compare the worth of traditional “free” complex libraries with the celebrated SESAME.
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Pulsic tools deployed by Toshiba for layout of next generation Flash Memory (Monday Sep. 28, 2009)
pulsic today announced that Toshiba Corporation will be extending its deployment of Pulsic tools and services in order to maximize efficiency and quality of results for the layout of their next generation Flash Memory designs.
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TSMC Selects Synopsys HSIM Simulator for Sub-40nm Memory IP Characterization (Monday Sep. 14, 2009)
Synopsys today announced that TSMC has adopted Synopsys' HSIM® hierarchical FastSPICE circuit simulator for its sub-40-nanometer (nm) memory intellectual property (IP) characterization flow.
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Mentor Graphics Launches Precise-IP Vendor-independent IP Platform for FPGA Design (Thursday Sep. 03, 2009)
Mentor Graphics today announced Precise-IP™ — a new vendor-independent IP (Intellectual Property) platform as part of the Mentor Graphics® Precision® Synthesis product line. The platform includes vendor-independent configurable IP from Mentor Graphics and links to categorized third-party IP from leading vendors.
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Cadence and GLOBALFOUNDRIES Announce Broad, Multi-Year Technology Agreement (Monday Aug. 31, 2009)
As part of the agreement, GLOBALFOUNDRIES has adopted a comprehensive suite of Cadence® technologies to aid in the design, verification and manufacturing of complex semiconductor devices targeting process technologies of 45 nanometers and below. In addition, GLOBALFOUNDRIES will team with the Cadence Services organization to build differentiated design-enablement capabilities to support customers at advanced process nodes.
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MindTree unfolds Verification Productivity Tool (Friday Aug. 28, 2009)
For an IP which does not have a legacy verification environment, building an environment takes a lot of time and effort. Re-usability, flexibility, scalability and less time to verify its functionality makes it even more challenging for a Verification engineer. MindTree’s VMM Template Code Generator (TCG) automates the creation of VMM based verification environment framework.
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VaST Enhances CoMET and METeor with OSCI TLM2 Support and Open SystemC Modeling Library (Tuesday Aug. 25, 2009)
VaST today announced the availability of the latest versions of its industry-leading virtual prototyping tools, CoMET® and METeor® version 6.3. CoMET is a system engineering tool enabling creation of software simulation-based virtual prototypes (VP) of a system-on-a-chip. METeor is an interactive, real-time software development environment for embedded systems and system-on-chip (SoC).