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Paradigm Works Releases Key Verification Productivity Software for the Open Verification Methodology (OVM) (Monday Aug. 17, 2009)
Paradigm Works announced today that it has made a key software contribution to the chip development community, donating its advanced SystemVerilog FrameWorksTM OVM Template Generator for free use through the Open Verification Methodology (OVM) World community website.
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Mentor Graphics Library of Questa Multi-view Verification Components Supports HDMI (Friday Aug. 07, 2009)
Mentor Graphics today announced that the Questa® Multi-view Verification Components (MVC) library now supports HDMI (High-Definition Multimedia Interface), a compact audio/video interface for transmitting uncompressed digital data.
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Arteris Introduces P-NoC to Address SoC Peripheral Interconnect Requirements (Monday Aug. 03, 2009)
Arteris today announced availability of the P-NoC™ peripheral interconnect solution, which provides an efficient way to integrate peripheral components into a System-on-Chip.
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Rockchip Collaborates with Synopsys and Chartered to Achieve First-Pass Silicon Success (Monday Aug. 03, 2009)
Rockchip Utilizes Chartered's 65nm Process and Synopsys' Technology and Services Portfolio For Tapeout of Next-Generation Multimedia SoC
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MindTree develops 'e' to SystemVerilog language migration utility (Tuesday Jul. 28, 2009)
SystemVerilog (SV) along with its methodologies is emerging as a unified language for design and verification using object oriented techniques. Companies who have already invested in Specman ‘e’ test benches face a dilemma whether to continue supporting legacy verification infrastructure for future versions of their products or migrate to SystemVerilog. Most of the leading EDA vendors support SystemVerilog as a part of the basic simulator with no additional tool cost. MindTree has developed a unique utility to reduce time and effort for migration as well as make verification easy and fast.
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Leading EDA Companies Join New ARM Fast Models Enablement Program (Tuesday Jul. 28, 2009)
ARM today announced that CoWare, Mentor Graphics and Synopsys Inc. have joined the ARM® Fast Models Enablement Program. Members of the Program are able to integrate fully validated Fast Models from ARM, for a range of ARM® processors, into their virtual platform environments and deliver to their customers.
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Magillem Releases its Verification Solution to Complement Its Existing Suite of Tools (Monday Jul. 27, 2009)
agillem the world leader in IP-XACT methodology tools today announced the availability of Magillem Verification Solution (MVS) to solve the verification complexity and bottleneck problem.
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Agnisys announces an innovative tool for Verification Management and Requirement Tracking (Monday Jul. 27, 2009)
Agnisys Inc. today announced IVerifySpec, a tool that ensures closure for Verification planning and execution. Using this tool and associated methodology, design/verification engineers and managers have a complete handle on the verification process.
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Calypto Delivers Fully Automated Sequential Optimization Flow for High-performance IP Blocks (Monday Jul. 27, 2009)
Enabled by Calypto’s SLEC RTL tool and new analysis capabilities in its proven PowerPro CG (clock gating) tool, Calypto’s Sequential Optimization Flow allows designers, for the first time, to use a fully automated flow to optimize power, area, and timing for high-performance IP blocks, such as microprocessors and digital signal processors (DSPs).
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MediaTek Deploys CoWare Solutions to Improve Product Development Cycle (Monday Jul. 27, 2009)
CoWare and MediaTek announced today that they have entered a multi-year, strategic relationship to deploy CoWare ESV solutions in MediaTek. The adoption allows MediaTek to expand their competitive market position through better trade-off between chip cost and architecture and as well as achieving better time to market.
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Sequence Launches PowerArtist-XP - Industry's First Automatic, Fully Integrated RTL Design For Power Platform (Monday Jul. 20, 2009)
Sequence Design today announced PowerArtist-XP. IP and SoC RTL designers, without becoming power experts, can analyze, visualize and reduce power by 10-60% or more within minutes on multi-million instances, with 50% fewer RTL edits, and productivity gains of 10X at a minimum.
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EdXact and Altos Partner to Improve IP Characterization Throughput (Wednesday Jul. 15, 2009)
Altos Design Automation Inc. and EdXact SA today announced that they are partnering to further improve characterization turn-around time especially for large cells and macro blocks.
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OneSpin's New Debug Automation Technology Boosts Formal Assertion-Based Verification Productivity (Wednesday Jul. 15, 2009)
OneSpin Solutions - provider of 360™ MV, the most comprehensive formal assertion-based verification (ABV) solution - today announced its new RootCauseAnalyzer™ that boosts formal ABV productivity by making SystemVerilog assertion (SVA) and RTL design debug much easier and faster.
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Duolog's Weaver breaks the SoC integration barrier (Tuesday Jul. 14, 2009)
Duolog Technologies, the Collaborative Design Automation Company, has announced the release of Weaver, an EDA tool for chip assembly that forms part of the Socrates Chip Integration Platform. Weaver is used to quickly and efficiently package and integrate the IP components of a system using rules-based integration, a methodology that promotes a formal method for System-on-Chip integration
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Satin IP Technologies, Toppan Photomasks and XYALIS Partner to Improve Design for Mask Manufacturing (Tuesday Jul. 14, 2009)
Satin IP, Toppan Photomasks and XYALIS have collaborated within the Crystal partnership program to significantly improve design for mask manufacturing (DFMM) by breaking the barriers that have traditionally separated integrated chip (IC) designers from mask shop engineers.
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Renesas Technology Halves SiP Design Time with SiP Top-Down Design Environment (Monday Jul. 13, 2009)
Renesas Technology Europe today announced the development of its SiP Top-Down Design Environment to boost efficiency when developing system in package (SiP) products combining multiple chips, such as system on chip (SoC) devices, MCUs, and memories, in a single package. It uses a top-down (predictive) design approach in which key characteristics, such as design quality and heat dispersion, are verified during the initial design stage.
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Satin IP Technologies Helps STMicroelectronics Achieve IP Design Quality Closure (Monday Jul. 13, 2009)
Satin IP Technologies, the company that delivers design quality closure with fast return on investment, has been working with the Home Entertainment and Display (HED) product group of STMicroelectronics on how to monitor and improve the quality of their internally developed semiconductor intellectual property (IP) blocks.
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Jasper Design Automation Introduces Multi-Proof JasperCore For Powerful, Scalable Formal Verification Deployment (Monday Jul. 13, 2009)
Jasper Design Automation announces its latest product, JasperCore. JasperCore harnesses the proven capabilities of the company’s formal analysis engines to boost productivity and decrease the cost of deployment by performing numerous parallel runs using ProofGrid™, a new capability that distributes formal technology.
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Oasys Design Systems Revolutionizes Synthesis for 20M+ Gate Designs (Monday Jul. 13, 2009)
Oasys Design Systems today came out of stealth mode operation to unveil "Chip Synthesis," a new EDA product category that company founders say reinvents RTL synthesis for chips beyond 20-million gates. The Oasys Chip Synthesis technology can synthesize an entire design from RTL to placed gates in a single bite, and do it in a fraction of the time. Leading-edge semiconductor companies worldwide have started using Oasys.
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Atrenta Collaborates With Sonics and Denali on a 1Team-Genesis Reference Flow to Accelerate SoC Assembly (Tuesday Jul. 07, 2009)
Atrenta today announced a collaboration with Sonics and Denali to build a reference flow based on Atrenta’s 1Team®-Genesis automated chip assembly product. The flow will facilitate a healthy eco-system of semiconductor IP that is qualified and ready to use in automated SoC assembly.
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Tieto Signs Long-Term Agreement to Deploy OneSpin Solutions' Formal Assertion-Based Verification Solution (Monday Jul. 06, 2009)
Tieto, a leading international IT and R&D services company, and OneSpin Solutions today announced a long-term agreement to deploy OneSpin’s 360 MV formal assertion-based verification (ABV) solution in Tieto’s high-end FPGA verification flow
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Synopsys MVSIM Adopted for Low Power Verification of STw8500 Mobile SoC Platform (Wednesday Jul. 01, 2009)
ST-Ericsson selected MVSIM for its proven ability to comprehensively verify low power techniques, including standby and built-in automated low power assertions, which enable the early detection of bugs. The tool's extensive support for the IEEE 1801 [Unified Power Format (UPF)] power format, on which the STw8500 project team has standardized, was also a deciding factor.
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Cadence and Xilinx Simplify SoC Development With Enterprise Verification Capabilities for FPGA Targeted Design Platforms (Wednesday Jun. 24, 2009)
IEEE-Standard Encryption for SecureIP Models Offers 2X Performance Boost; Open Verification Methodology (OVM) to Increase Schedule Predictability and Quality
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Synopsys and TSMC Deliver Accurate Lithography Verification for 28nm Designs (Tuesday Jun. 23, 2009)
Synopsys today announced the results of a collaboration with TSMC under TSMC's Unified Design-for-Manufacturing (UDFM) architecture effort. This collaboration enables designers to improve yields and accelerate time to market through more accurate lithography simulation at 28 nanometer (nm) and below.
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SMIC and Synopsys Announce the Availability of Reference Flow 4.0 (Tuesday Jun. 23, 2009)
The reference flow, the result of collaboration between Synopsys Professional Services and SMIC, adds the Synopsys Eclypse™ Low Power Solution and IC Compiler Zroute technology, expanding the resources available to designers to address low power and design-for-manufacturing challenges at smaller process nodes.
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UMC Qualifies Comprehensive Mentor Graphics Silicon Test Suite for its 65nm and 40nm IC Reference Flows (Tuesday Jun. 23, 2009)
Mentor Graphics today announced that its silicon test and diagnosis suite has been validated by UMC for use in its 65 and 40 nanometer reference flows. The foundation of this comprehensive silicon test flow is the TestKompress® automated test pattern generation (ATPG) solution for achieving high test quality with the lowest test cost.
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SpringSoft and TSMC Commence Joint Development of Multi-Node Process Design Kit Portfolio (Monday Jun. 22, 2009)
SpringSoft today announced a multi-year technology agreement with TSMC to jointly develop and validate process design kits (PDKs) for leading-edge chip manufacturing technologies.
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Calypto Delivers Industry's First Automated Tool for Memory Power Optimization (Monday Jun. 22, 2009)
Calypto announced the availability of its PowerPro MG (memory gating) tool. The new tool is the industry’s first product that automatically generates power-optimized RTL by taking advantage of the low-power modes available in today’s leading on-chip memories.
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Tiempo Demonstrates the First Asynchronous Synthesis Tool Using Standard Languages (Friday Jun. 19, 2009)
Tiempo will reveal at the 46th DAC, its unique and breakthrough asynchronous synthesis tool. ACC (“Asynchronous Circuit Compiler”) is the first synthesis tool on the market which automatically generates asynchronous and delay-insensitive circuits from a model written in a standard hardware description language.
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SystemVerilog FrameWorks VMM Template Generator Upgraded for VMM 1.1 (Friday Jun. 19, 2009)
Paradigm Works today announced VMM 1.1 enhancements to its SystemVerilog FrameWorks™ VMM Template Generator software. The VMM Template Generator takes user input parameters and automatically creates a functional framework for a VMM-compliant verification environment.