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Synopsys and Actel Renew OEM Relationship for FPGA Design Software (Wednesday Jun. 17, 2009)
Under the terms of the agreement, Actel maintains rights to provide Actel-specific versions of Synopsys' Synplify Pro®, Identify® and Synplify® DSP software as part of the Libero® Integrated Design Environment (IDE).
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Silistix Extends Its Industry Leading Asynchronous CHAIN(R)works Product Family With the Introduction of CHAINworks Sync (Tuesday Jun. 16, 2009)
CHAINworks Sync enables architects and designers to synthesize Networks-on-Chip using conventional synchronous circuit techniques thereby allowing mainstream chip designs to leverage the industry-leading predictability of Silistix' CHAINworks methodology.
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Socle Adopts Platform Core Compiler to Accelerate Customer SoC Design (Tuesday Jun. 16, 2009)
Socle adopts this proprietary automation environment, Socle SoC Platform Core Compiler, under IP-XACT protocol to greatly save IP integration time as well as minimize possible errors and shorten iteration time period. It hence saves 70% time and still delivers high quality design to customer.
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Paradigm Works Distributes ReleaseWorks As Free, Open Source Software (Tuesday Jun. 16, 2009)
Paradigm Works today announced that its best-in-class release management software, ReleaseWorks®, is now available as free, open source software.
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Arteris and Duolog Streamline SOC Integration Design Flow (Monday Jun. 15, 2009)
Arteris and Duolog today announced the integration of Duolog design tools with Arteris’ NoC solution to provide designers a more streamlined and efficient way to integrate multiple semiconductor intellectual property (IP) blocks on a single system on chip (SoC) device.
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Agnisys announces free download of a smart IP Documentation tool (Monday Jun. 15, 2009)
Agnisys Inc. today announced a free version of its flagship product IDesignSpecTM, for hardware development. IDesignSpecTM reduces the effort required to create hardware specifications and provides for the management of register data throughout the design process.
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Synopsys Continues Galaxy Custom Designer Momentum with 2009.06 Release (Monday Jun. 15, 2009)
Synopsys today announced availability of advanced analog simulation and layout capabilities in its Galaxy Custom Designer™ implementation solution. The new features in the 2009.06 release deliver productivity advances to aid analog circuit designers and layout engineers, enabling Synopsys to further extend its reach in the custom implementation segment.
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TSMC Selects Synopsys Galaxy Implementation Platform for Integrated Sign-off Flow (Tuesday Jun. 09, 2009)
The RTL-to-GDSII design flow deploys the advanced optimization technologies of Synopsys' Design Compiler® synthesis and IC Compiler physical implementation solutions, and the PrimeTime® sign-off and Star-RCXT™ extraction solutions - the industry yardsticks for IC design sign-off.
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TSMC Selects Legend's Model Diagnoser for Standard Cell Library Quality Assurance (Tuesday Jun. 09, 2009)
Legend Design Technology, Inc. today announced that its Model Diagnoser has been selected by TSMC for use in the quality assurance of the company’s standard cell libraries.
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Casio Selects Cadence C-to-Silicon Compiler for High-Level Synthesis (Monday Jun. 08, 2009)
Cadence today announced that Casio Computer Co., Ltd., has selected the Cadence® C-to-Silicon Compiler as its high-level synthesis solution.
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DeFacTo Demonstrates to TESSOLVE the Effectiveness of its RTL Testability Sign-off Solution (Friday Jun. 05, 2009)
DeFacTo Technologies S.A. today announced that its RTL testability sign-off solution called HiDFT-Scan, has been successfully evaluated by TESSOLVE in India.
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Dolphin Integration launches the design of a SoC as an Archipelago for leakage control with the PERK cell Library (Thursday Jun. 04, 2009)
Dolphin Integration complements the High Density stem HD-BTF of the SESAME library with the solution of choice for leakage reduction.
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SMIC Deploys Synopsys HSPICE Simulator for 45-nm Physical IP and Standard Cell Development (Tuesday Jun. 02, 2009)
Synopsysb today announced that SMIC has adopted Synopsys' HSPICE® circuit simulator and WaveView Analyzer for design and verification of their 65-nanometer (nm) and 45-nm IP blocks, I/O circuitry and standard cell characterization flows.
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ELMOS Semiconductor and Dolphin Integration cooperate for innovation in schematics edition (Monday May. 25, 2009)
ELMOS and Dolphin Integration announce they have completed together a major joint project for innovating in schematic edition, commercialized by Dolphin Integration under the name of SLED.
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Cadence Speeds Systems Development with Automated Transaction-Level Verification (Tuesday May. 19, 2009)
Cadence announced today that it has delivered an extended system-level verification solution that supports the Open SystemC Initiative (OSCI) TLM 2.0 standard.
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SpringSoft Introduces Structured Method for SystemVerilog Testbench Debug and Analysis (Monday May. 18, 2009)
SpringSoft today announced SystemVerilog Testbench (SVTB) debug support with the latest release of its VerdiTM Automated Debug System.
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NXP Semiconductors Accelerates Design Cycle using New Cadence Encounter Digital Implementation System for Industry’s First 45nm Digital TV Processor (Monday May. 18, 2009)
Cadence Design Systems announced today that NXP Semiconductors utilized the new Cadence® Encounter® Digital Implementation System (EDI System), and its seamless design-for-manufacturing (DFM) technologies to ensure reliable production of its advanced 45-nanometer PNX85500 digital TV processor chip with a significant acceleration in productivity.
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New patented solutions from Dolphin Integration for pop-up noise reduction (Friday May. 15, 2009)
Designers must face the challenge of managing the growing complexity in audio systems due to the progress of audio technology, while ensuring the overall quality of systems, especially for high definition applications. As a consequence, undesirable noises such as pop-up have to be removed or avoided.
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Toshiba Selects Synopsys as Its Key EDA Partner (Tuesday May. 12, 2009)
Synopsys today announced that Toshiba has signed a multi-year business agreement to establish Synopsys as its key EDA partner across the Toshiba semiconductor design flow.
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Synopsys Launches IC Validator, Offers Significant Reduction in Physical Verification Turnaround Time for Advanced Designs (Monday May. 11, 2009)
Synopsys, Inc. , a world leader in software and IP for semiconductor design and manufacturing, today announced the IC Validator DRC/LVS solution for in-design physical verification and signoff for advanced designs at 45 nanometer (nm) and below.
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Cadence Encounter Digital Implementation System Used by Gennum’s Snowbush IP Group to Speed Delivery of Industry’s First 45nm USB 3.0 PHY IP (Thursday May. 07, 2009)
Cadence announced today that Gennum Corporation’s Snowbush IP Group utilized the Cadence® Encounter® Digital Implementation System to develop the industry’s first 45-nanometer SuperSpeed USB 3.0 PHY IP core.
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EDA Consortium Conducts Multi-Faceted Investigation into EDA Software Piracy (Wednesday May. 06, 2009)
The EDA Consortium is working with multiple companies in the anti-piracy field to investigate EDA software piracy from multiple aspects.
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Paradigm Works Announces VMM 1.0 enhancements to its SystemVerilog FrameWorks VMM Template Generator software (Monday May. 04, 2009)
Paradigm Works today announced VMM 1.0 enhancements to its SystemVerilog FrameWorks™ VMM Template Generator software. The VMM Template Generator takes user input parameters and automatically creates a functional framework for an VMM compliant verification environment.
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Agnisys IncEDA startup announces innovative tool for register management of IP and SoCs (Friday May. 01, 2009)
Agnisys today announced the release of IDesignSpecTM(IDS), a new tool for Register Management and Automation for hardware designs. IDS decreases the time and effort to specify hardware registers and automates the generation of data required by RTL design, verification, diagnostic, software and lab debug.
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Toshiba Exceeds Quality Goals for 65-nm Multimedia Chips Using Synopsys Test Solution (Wednesday Apr. 29, 2009)
Synopsys today announced that Toshiba deployed Synopsys' test solution to exceed the rigorous quality demands for its 65-nanometer (nm) multimedia chips. Toshiba engineers employed Synopsys' TetraMAX® automatic test pattern generation (ATPG) solution to achieve ultra-high test quality.
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Tego Standardizes on VMM and Synopsys VCS Solution to Speed Verification of Radio Frequency Identification Tags (Tuesday Apr. 28, 2009)
Synopsys today announced that Tego, Inc. has standardized on the production-proven VMM verification methodology and VCS® functional verification solution, both key components of Synopsys' Discovery™ Verification Platform, to verify their radio frequency identification (RFID) tags for the aviation industry.
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Jasper, AMD Ink Long-Term Formal Verification Deal (Tuesday Apr. 28, 2009)
Jasper Design Automation today announced it has signed a long-term agreement with AMD to place JasperGold formal verification technology in AMD design centers worldwide.
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SpringSoft, UMC Support Custom Chip Design with 65nm Process Design Kit (Monday Apr. 27, 2009)
SpringSoft and UMC today announced immediate availability of the foundry-certified Laker™ process design kit (PDK) for UMC 65-nanometer (nm) manufacturing technologies.
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Magillem Design Services announces release of new Generation Register View (Monday Apr. 27, 2009)
A brand new tool, innovative and cost competitive, allowing for collaborative Register Management with synchronization and hierarchical description features.
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TÜV NORD - IFM and Dolphin Integration announce their partnership for VHDL-AMS modeling and verification with SLED and SMASH (Monday Apr. 27, 2009)
he Institute for Vehicle Technology (IFM) of the TÜV NORD, one of Europe's largest technical service providers, has selected the multi-domain and multi-level simulator SMASH from DOLPHIN Integration for VHDL-AMS modeling and verification.