English
| |
-
Jasper Patent Speeds Debug During Verification (Friday Apr. 17, 2009)
Jasper Design Automation today announced it has been awarded U.S. Patent No. 7,506,288 for “interactive analysis and debugging of a circuit design during functional verification of the circuit design.”
-
Satin IP Technologies to Demonstrate First Product to Comply with Emerging IEEE Quality IP Metric Standard (Thursday Apr. 16, 2009)
Satin IP Technologies has been working with the Quality of Electronic and Software Intellectual Property (QIP) Metric standard working group of the IEEE Design Automation Standards Committee (DASC) since the emerging standard was donated to the IEEE by VSIA.
-
NXP Adopts Mentor Graphics’ Veloce Hardware Emulator to Accelerate Time-To-Market for their HDTV and Set-Top-Box Chip Sets (Wednesday Apr. 15, 2009)
Mentor Graphics today announced that NXP, the independent semiconductor company founded by Philips, has adopted the Veloce® platform for the complete system-level verification of its next generation of digital Systems-on-Chip (SoC) for High-Definition TV (HDTV) and Set-Top-Box (STB).
-
Synopsys PrimeTime Advanced On-chip Variation Analysis Enables Renesas to Accelerate Timing Closure at 65-nm and Below (Tuesday Apr. 14, 2009)
Synopsys today announced that Renesas Technology has deployed Synopsys' PrimeTime® advanced on-chip variation (OCV) capability to help accelerate timing closure for 65-nanometer (nm) and below system-on-chip (SoC) designs.
-
Priva Technologies Integrates Synopsys Galaxy Custom Designer Solution Into SoC Design Flow (Monday Apr. 13, 2009)
Synopsys today announced that Priva Technologies has adopted Synopsys' Galaxy Custom Designer(TM) custom implementation solution to design its next-generation security system-on-chip (SoC) integrated circuits (ICs).
-
Synopsys Introduces Discovery 2009 Delivering Faster, Unified Verification Solutions (Monday Apr. 06, 2009)
Platform Encompasses New Multicore Simulation Performance, Native Design Checks and Comprehensive Low Power Verification Capabilities
-
IMEC unveils tools to speed design of energy-efficient multi-processor SoC platforms (Wednesday Apr. 01, 2009)
IMEC unveils a suite of tools and methods to optimize the mapping of applications on embedded multiprocessor system-on-chip (MPSoC) platforms
-
Cadence and NEC Electronics Announce Encounter Digital Implementation System To Support NEC Electronics' System LSI with Built-In V850 CPU Core (Tuesday Mar. 31, 2009)
NEC Electronics developed its LSIs next-generation CPU core, successfully reducing the total design turnaround time (TAT) by fifty percent while including complete full multi mode, multi-corner analysis and optimization throughout the back end of the design flow.
-
Mentor and NXP Achieve Major Milestone in Silicon Test Partnership (Thursday Mar. 26, 2009)
A manufacturing test flow that integrates the Mentor TestKompress® ATPG product has been released to NXP designers worldwide following a comprehensive development, integration and qualification project. The new flow is designed to meet NXP's requirements for test quality and provides the highest pattern compression available.
-
Sequans Speeds Tapeout of 65-Nanometer Mobile WiMAX Single Die Baseband Chip with Cadence Low-Power Solution (Wednesday Mar. 25, 2009)
Cadence announced today that Sequans Communications, an industry leader in fixed and mobile WiMAX chipmaker, has used the Cadence® Low-Power Solution to implement innovative power-efficient design techniques into its newest 65-nanometer Mobile WiMAX baseband and RF single die chip
-
Jasper Extends Formal Verification Technology Lead With Four New Patents (Wednesday Mar. 25, 2009)
Jasper Design Automation, provider of advanced formal technology solutions, today announced it has been awarded four new U.S. patents.
-
Cadence Enhances Low-Power Solution Enabling More Predictable Power-Efficient Design (Monday Mar. 16, 2009)
Cadence announced today that the Cadence® Low-Power Solution has been enhanced to include support for new on-chip power management schemes enabled by the recently ratified Si2 Common Power Format (CPF) Version 1.1.
-
Synopsys Announces Yield Explorer - Design-Centric Yield Management for Product Engineering Teams (Monday Mar. 16, 2009)
Synopsys, Inc. , a world leader in software and IP for semiconductor design and manufacturing, today introduced Yield Explorer, a new yield management product that expedites the discovery and mitigation of yield limiters in leading-edge integrated circuits.
-
Synopsys Introduces Lynx Design System (Monday Mar. 16, 2009)
Synopsys today announced the immediate availability of its Lynx Design System, the industry's most comprehensive and highly automated environment for implementing chips. Designed for scalable use in design organizations of all sizes, the Lynx Design System combines a production-proven RTL-to-GDSII design flow with productivity-enhancing features to accelerate chip development while mitigating the risks of designing at new process nodes.
-
Zocalo Tech, Inc. Introduces First EDA Tool Dedicated to Assertion Library Productivity (Wednesday Mar. 04, 2009)
Zocalo Tech, Inc., an Austin, Texas startup, is introducing Zazz, a productivity tool for use with assertion libraries. The initial release supports Accellera’s Open Verification Library (OVL) and Cadence’s Incisive® Assertion Library (IAL).
-
OVM Extended to Efficiently Manage Coverage Metrics (Thursday Feb. 26, 2009)
Mentor Graphics and Cadence Design Systems today announced they have extended the Open Verification Methodology (OVM) to include the Unified Coverage Database (UCDB) application program interface (API) and an XML interchange format.
-
Certess Announces The First C-Level Functional Qualification Tool (Tuesday Feb. 24, 2009)
Certess today announced Certitude-C, the next generation of its functional qualification software product for companies developing SoCs or integrating intellectual property (IP) blocks using C.
-
Synopsys, Powerchip and Nikon Collaborate on 42-nm Flash Memory Optimization (Tuesday Feb. 24, 2009)
Synopsys today announced a joint collaboration with Powerchip and Nikon to deploy the Nikon Scanner Signature Files (NSSF) as a means to increase Proteus ProGen model accuracy on 42-nanometer (nm) flash memory designs.
-
Jasper Design Automation Introduces Design Activation Services To Promote IP and Design Reuse, Driving Higher Customer ROI (Monday Feb. 23, 2009)
Jasper Design Automation today announced its Design Activation Services to help both design houses and commercial IP vendors reap the benefits of design and IP reuse, amortizing research and development costs over multiple IC design projects.
-
DOLPHIN Integration extends SoC GDS capabilities to include OASIS reading and writing (Monday Feb. 16, 2009)
DOLPHIN Integration announces the availability of the latest release of its SoC GDS layout analysis and processing solution which includes the capability to read and write layout databases in OASIS format.
-
Legend's MSIM SPICE Circuit Simulator Certified for TSMC's Advanced Nanometer Circuit Designs (Wednesday Feb. 11, 2009)
Legend Design today announced that its MSIM® circuit simulator has been qualified through TSMC’s 40 nanometer (nm) Spice Tool Qualification Program. The program provides designers the ability to select qualified SPICE simulators to match their design needs, improve compliance with processes technology, and ensure design accuracy for first time silicon success
-
Synopsys Defines Next Era of Rapid Prototyping (Monday Feb. 09, 2009)
Synopsys today introduced its expanded Confirma™ rapid prototyping platform. The addition of the recently acquired CHIPit® products, tools and technologies simplifies the implementation and deployment of rapid prototypes, allowing users to begin hardware-assisted system validation and embedded software development sooner.
-
Mentor Graphics Extends High Level Synthesis Leadership with Acquisition of Agility Design Solutions Inc. C Synthesis Suite (Friday Jan. 23, 2009)
Mentor Graphics today announced completion of the acquisition of the C synthesis assets of Agility Design Solutions Inc. These tools were formerly owned and marketed by Celoxica Holdings.
-
Cadence Expands C-to-Silicon Compiler with High-level Synthesis Support for Altera and Xilinx FPGAs (Wednesday Jan. 21, 2009)
Cadence today announced the integration of FPGA-synthesis for Altera and Xilinx FPGAs with the Cadence® C-to-Silicon Compiler, its flagship electronic system-level (ESL) technology for hardware design and implementation.
-
Blue Pearl Software Introduces "No EDA Tool Purchase Plan" (Wednesday Jan. 21, 2009)
Blue Pearl Software introduces an innovative EDA business model designed to emphasize affordability by offering access to productivity enhancing tools at a fraction of their purchase price. The program offers short term use of the company's tools without incurring the high cost of purchasing, integrating, and learning new tools. The products included in the offer are Indigo RTL Analysis, Cobalt Timing Constraint Generation, and Azure Timing Constraint Validation.
-
New Capabilities in Synfora Algorithmic Synthesis Design Tools Increase Performance, Decrease Area (Tuesday Jan. 20, 2009)
Synfora today announced versions of its PICO Extreme™ and PICO Extreme FPGA algorithmic synthesis design tools that will achieve higher performance and smaller area than the previous generation of the tools.
-
Jasper Design Automation Announces ActiveDesign With Behavioral Indexing for Greater RTL Design Quality and Designer Productivity (Monday Jan. 19, 2009)
Powered by formal analysis and Jasper’s new Behavioral Indexing technology, ActiveDesign delivers dramatic breakthroughs in design comprehension, driving higher RTL design quality and greater designer productivity. Jasper’s Behavioral Indexing technology enables ActiveDesign to iteratively extract, index and store relevant design behaviors, along with the RTL, in a dynamic, executable database referred to as the Activated Design™.
-
OneSpin Mainstreams Comprehensive Formal Assertion-Based Verification Enabling Step-by-Step Approach to Adoption and Use (Monday Jan. 19, 2009)
New OneSpin 360® MV Product Family Provides Choice of Entry/Exit Points Tailored to Users Project Needs and Experience; New Diagnosis Technology Slashes Debug Effort for Complex SystemVerilog Assertions
-
Mentor Graphics Supports Fujitsu to Implement Open Verification Methodology (OVM) (Thursday Jan. 15, 2009)
Fujitsu and Fujitsu Laboratories adopted the IEEE Std. 1800-2005 SystemVerilog language and the OVM to verify a complex, multi-clock domain SoC that can form a key element of Fujitsu’s high-performance parallel computer system. Fujitsu’s and Fujitsu Laboratories’ verification environment features an advanced UML front-end to the OVM that facilitates specification driven verification of multiple SoCs. The design specification is analyzed to extract use cases systematically and exhaustively that form verification scenarios.
-
MoSys Picks Real Intent for IP Verification, Timing Closure (Thursday Jan. 15, 2009)
Real Intent announced that MoSys has selected Real Intent's Meridian CDC(TM) software for the verification and sign-off of Clock Domain Crossings (CDC) for its semiconductor IP solutions.