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Ultra-low power 32 kHz RC oscillator designed in GlobalFoundries 22FDX
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Mentor Graphics Supports Fujitsu to Implement Open Verification Methodology (OVM) (Thursday Jan. 15, 2009)
Fujitsu and Fujitsu Laboratories adopted the IEEE Std. 1800-2005 SystemVerilog language and the OVM to verify a complex, multi-clock domain SoC that can form a key element of Fujitsu’s high-performance parallel computer system. Fujitsu’s and Fujitsu Laboratories’ verification environment features an advanced UML front-end to the OVM that facilitates specification driven verification of multiple SoCs. The design specification is analyzed to extract use cases systematically and exhaustively that form verification scenarios.
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MoSys Picks Real Intent for IP Verification, Timing Closure (Thursday Jan. 15, 2009)
Real Intent announced that MoSys has selected Real Intent's Meridian CDC(TM) software for the verification and sign-off of Clock Domain Crossings (CDC) for its semiconductor IP solutions.
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Cadence Low-Power Solution Enables Fujitsu Microelectronics Tapeout of 65nm WiMAX Design (Monday Jan. 12, 2009)
Cadence Design Systems announced today that Fujitsu Microelectronics Limited has taped out a 65nm mobile WiMAX design using Fujitsu Reference Design Flow 3.0, which includes Common Power Format (CPF) enabled Cadence® Low-Power technologies.
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Dolphin Integration announces four times faster VHDL-AMS simulation with SMASH (Monday Dec. 22, 2008)
DOLPHIN Integration announces the immediate availability of an update to SMASH 5.11 which delivers up to a four-fold acceleration of VHDL-AMS simulation speed compared to previous releases for complex models using vectors and matrices.
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Synopsys and STMicroelectronics Accelerate 32-Nanometer Readiness Delivering Optimized Standard Cell Library and Route-Rule Validation in IC Compiler (Friday Dec. 19, 2008)
Synopsys today announced early results of its 32-nanometer (nm)-centric joint collaboration with STMicroelectronics, a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications.
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Cadence Provides Open Source OVM Adoption Solution for VMM Users in Response to Industry Demand (Thursday Dec. 04, 2008)
Cadence Design Systems today announced the release of an open-source SystemVerilog solution to help users include Synopsys' Verification Methodology Manual verification IP (VMM VIP) as they adopt the advanced environments supported by the Open Verification Methodology (OVM).
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Mentor Graphics Delivers Solution for SystemVerilog Base Class Library Interoperability to Enable Reuse of Legacy VMM Code in an OVM Environment (Thursday Dec. 04, 2008)
The solution enables the easy and flexible reuse of legacy Verification Methodology Manual (VMM) code within an OVM environment.
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Creative Chips Adopts Synopsys' Galaxy Custom Designer Mixed-Signal Implementation Solution (Monday Nov. 24, 2008)
Custom Designer provides a comprehensive digital and analog design flow that helped enable Creative Chips to implement complex product designs and meet critical time-to-market, cost, and quality constraints.
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Agilent Technologies Announces Industry's First Licensing Model Dedicated to Advanced Verification for RFICs (Thursday Nov. 20, 2008)
Used with Agilent's GoldenGate RFIC simulation, analysis and verification software suite, the new license helps manage costs and improves large-scale RFIC yield and manufacturability.
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OCP-IP Releases New OCP Checker as Part of CoreCreator II Tool (Wednesday Nov. 19, 2008)
The OCP checker is the premier fourth-generation solution for validating protocol compliance of master and slave devices communicating utilizing OCP. It is based on SystemVerilog assertions (SVA) and can be used with all major logic simulator
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Synopsys Unveils Breakthrough Modeling Technology to Address Library Data Size Explosion at 45-nm and Below (Wednesday Nov. 19, 2008)
Enhanced Composite Current Source (CCS) Modeling Technology Reduces Library Data Size by 75 Percent; Improves EDA Tool Efficiency by up to 60 Percent
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Aldec Releases Unified 64-bit Multi-Threaded HDL Design Environment (Monday Nov. 17, 2008)
Riviera-PRO 2008.10 delivers a powerful new multi-threaded Graphical User Interface (GUI) with post-simulation debugging, SystemC/C/C++ and HDL co-debugging, support for SVA/ PSL/OVA Assertions and Functional Coverage in the Waveform Viewer, all in one Design Environment.
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Calypto Announces New SLEC Release for Comprehensive Verification of Wireless, Video, Image Processing System-on-Chip Designs (Tuesday Nov. 11, 2008)
Calypto Design Systems announced today the latest version of SLEC supports fixed-point datatypes and system-level memory interfaces commonly used in wireless, video and image processing system-on-chip (SoC) designs.
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Atrenta Announces "SpyGlass(R) Clean" Flow with Leading ESL Synthesis Providers (Monday Nov. 10, 2008)
SpyLinks(TM) Program Initiative Enables High Quality Register Transfer Level (RTL) Output from Electronic System Level (ESL) Synthesis Tools
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Real Intent Introduces Meridian FPGA, Popular Clock Domain Crossing Verification Software for Altera Customers (Wednesday Nov. 05, 2008)
Meridian FPGA is specifically designed to work with Altera Corporation’s latest release of its Quartuss® II software, version 8.1, to verify Clock Domain Crossings (CDC).
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Mentor Graphics Olympus-SoC Place-and-Route System Slashes Design Closure Times with Industry's First Parallel Timing Analysis and Optimization Technology (Monday Oct. 13, 2008)
Mentor today announced the availability of new task-oriented parallelism technology in the Mentor Graphics Olympus-SoC™ place-and-route system that allows timing analysis and optimization tasks to run in parallel to deliver up to 7X improvement in timing analysis run times, and up to 4X improvement in design closure times using eight CPU cores.
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Cadence Collaborates With ARM to Deliver Hardware/Software Emulation Environment, Accelerating Processor-Based Design (Tuesday Oct. 07, 2008)
Cadence Design Systems announced today the availability of an ARM hardware/software co-verification environment that accelerates the system validation process and provides mutual customers with a faster path to first silicon working with early software.
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GateRocket Ships Advanced FPGA Verification Solution for Virtex-5 FPGA (Thursday Oct. 02, 2008)
The RocketDrive cuts verification and in-system debug time for advanced single or multi-FPGA based projects while adding significant value through seamless integration to a design team’s existing design verification environment, without a change in design flow or verification methodology.
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Numetrics Enhances NMX-ERP Software Suite With Extensive Customization Capability (Wednesday Sep. 24, 2008)
Numetrics announced release 3.1 of its NMX-ERP(TM) suite. This version significantly improves user productivity, allowing customization of data entry, project planning models and analysis reports.
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OKI Network LSI Reduces Test Time 90% by Combining the Open Verification Methodology (OVM) and Cadence Incisive Technologies (Wednesday Sep. 24, 2008)
OKI Network LSI Co., Ltd., is reporting significant benefits from its use of the Open Verification Methodology (OVM) with Cadence Incisive functional verification technology. Co-developed by Cadence and released last year, the OVM is the first scalable, open, multi-vendor verification methodology for SystemVerilog in the industry.
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Infiniscale and Mentor Graphics collaborate with STMicroelectronics to offer a unique design solution for analog parametric yield optimization (Tuesday Sep. 23, 2008)
Infiniscale and Mentor Graphics announced today a collaboration to provide innovative parametric yield optimization to the sub-90nm analog designers’ community, in cooperation with STMicroelectronics, their common major customer.
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Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach (Monday Sep. 22, 2008)
Engineers at STMicroelectronic have revealed how to use domino logic, a very fast circuit design style utilized in the highest performance custom designs,in an automated framework.
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Synopsys Enters Mixed-Signal Implementation Market With Galaxy Custom Designer (Monday Sep. 22, 2008)
Architected for productivity, Galaxy Custom Designer leverages Synopsys' Galaxy™ Design Platform to provide a unified solution for custom and digital designs, thereby enhancing designer efficiency.
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New Release of the OVM Takes Verification to the Next Level (Thursday Sep. 11, 2008)
The new release extends the proven sequential stimulus mechanism in the OVM with transaction-level modeling (TLM) interfaces to improve the modularity and reuse of stimulus sequences. Other enhancements include direct support for parameterized classes in the OVM factory and built-in debug support for TLM connections throughout the hierarchy.
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Sequence, Faraday, NemoChips Team To Slash Over 50% Of Total Power From Advanced Mobile Processor Design (Thursday Sep. 11, 2008)
Pairing Sequence Design's PowerTheater, and the low-power design expertise of NemoChips and Faraday Technology Corporation, led to a 52 percent reduction in total power for an advanced mobile processor design.
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Cadence Introduces SaaS Solutions for Semiconductor Design (Wednesday Sep. 10, 2008)
These production-proven, ready-to-go design environments are accessible via the Internet and provide design teams a faster time-to-productivity with reduced risk and cost. Cadence Hosted Design Solutions are available for custom IC design, logic design, physical design, advanced low power, functional verification, and digital implementation.
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Tensilica Collaborates with Cadence to Create CPF-Enabled Flow for Tensilica’s Multimedia Subsystems (Tuesday Sep. 09, 2008)
Tensilica announced today that they have collaborated with Cadence to create a Common Power Format (CPF)-enabled low-power reference design for a multimedia subsystem based upon its popular 330HiFi Audio Processor and 388VDO Video Engine
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Cadence Expands Enterprise Verification Solution to Include Planning, Unified Verification Metrics and Industry Databases (Tuesday Sep. 09, 2008)
With these enhancements, project managers can now more easily create verification plans, expand the scope and scalability of project metrics being managed, and uniquely combine formal verification, testbench simulation, and verification acceleration metrics for integrated verification process management.
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Cadence Extends Low-Power Leadership With Early Dynamic Power Analysis and Pre-RTL Exploration (Monday Sep. 08, 2008)
In Breakthrough for System-Level Design, Cadence Reveals Technologies to Enable Early Exploration of Chip and System Power Requirements
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Certess Certitude Increases Verification Quality at Mellanox Technologies (Thursday Sep. 04, 2008)
Certitude is the first commercial functional qualification software product for companies developing systems on a chip (SoCs) or integrating intellectual property (IP) blocks. Certitude certifies that if a semiconductor chip design had a bug, it would be found.