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Leading European Design Consulting Firms Standardize on VMM Verification Methodology (Tuesday Aug. 26, 2008)
Chipright, CreVinn and Verilab Speed Chip Development with VMM Methodology
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Magma Titan Analog Migration Solution Ports Rambus Custom Designs (Monday Aug. 25, 2008)
This joint effort led to the design, porting and tape out of complex, high-performance analog circuits for Rambus' leadership XDR(tm) memory and FlexIO(tm) processor bus architectures.
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EMCoS and Dolphin Integration announce easy to use VHDL-AMS for EMC and Signal Integrity simulation thanks to the bundling of EMC Studio and SMASH (Monday Aug. 18, 2008)
EMCoS and DOLPHIN Integration announce their solution for EMC and Signal Integrity simulation in automotive electronics applications.
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Open Verification Methodology Helps KPIT Cummins Boost Productivity, Shorten Turnaround Time (Thursday Jul. 31, 2008)
The OVM, which Cadence Helped Develop, Enabled KPIT Cummins to Quickly Find Bugs in Its IP Design
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OKI Turns to Cadence and the Open Verification Methodology (OVM) to Speed Product Development (Tuesday Jul. 29, 2008)
OVM Enables OKI to Improve Verification IP Integration and Compress Testbench Development by 30%
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Toshiba announces co-design/co-verification platform for collaborative development of chip, package and PCB system (Tuesday Jul. 29, 2008)
The CPS (Chip-Package-System) codesign/ co-verification platform supports the rapid identification of the optimum SoC package as well as delivering the cost/performance benefits and improving verification accuracy prior to hardware prototyping.
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Complete SoC development environment now available at OpenCores (Thursday Jul. 17, 2008)
OpenCores has made available a "Virtual Ubuntu Linux" installation which installs and configures a VMWare virtual machine. It includes all of the tools necessary to start hardware and software development on a OpenRISC platform.
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Dolphin Integration announces the availability of the major release of Power Consumption Analyzer SCROOGE 2.0. (Friday Jul. 11, 2008)
SCROOGE is the first EDA solution to provide the capability to analyze hierarchically the total power consumption of your mixed signal SoC.
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Mentor Graphics Delivers High-Performance Platform for the Accelerated Verification of PCI Express Applications (Wednesday Jun. 25, 2008)
The platform consists of the Veloce® family of hardware-assisted verification products and the iSolveTM PCI Express product, which provides a cost-effective and efficient solution, delivering a dynamic and accurate PCI Express verification environment.
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Mentor Graphics Delivers High-Performance Platform for the Accelerated Verification of Multimedia Applications (Tuesday Jun. 17, 2008)
The platform consists of the Veloce® family of hardware-assisted verification products and the iSolveTM Multimedia product, which provides a cost-effective and efficient solution, delivering a dynamic and accurate multimedia verification environment.
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Cadence Enhances RF Verification With High-Performance 'Turbo' Technology and Comprehensive Electromagnetic Analysis (Monday Jun. 16, 2008)
Customers Benefit From 2-5X Faster RF Analysis With Virtuoso Spectre Turbo Technology, and Fast and Accurate Electromagnetic Analysis Delivered by Virtuoso RF Designer
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Synopsys' Synplicity Business Group Announces New Products and Product Enhancements Providing Designers With a Faster Path to Silicon (Tuesday Jun. 10, 2008)
Synplify Premier for Altera Devices, Identify Pro Debug Tool Production Release, and New HAPS Prototyping System Among Many New Designer Benefits Featured at DAC
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Target Compiler Technologies Announces Key Design Wins and New Positioning (Tuesday Jun. 10, 2008)
Target Compiler Technologies™, the leader in tools used for designing and programming application-specific processors (ASIPs), today announced several new design wins and also its new positioning.
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Synopsys Delivers 45-Nanometer Low Power Reference Flow for Common Platform Technology Validated with ARM Physical IP (Monday Jun. 09, 2008)
Comprehensive Flow Enhanced with Integration of Eclypse Low Power Solution Enabled by Unified Power Format
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Synopsys and UMC Release 65-Nanometer Low Power Design Flow Enabled by the Unified Power Format (Monday Jun. 09, 2008)
Power management capabilities enhanced with integration of Eclypse Low Power Solution
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Cadence Collaborates with UMC to Deliver 65nm CPF-Based Low-Power Reference Design Flow (Monday Jun. 09, 2008)
CPF-Based 65nm Low-Power Reference Design Flow Address Complex Design Issues and Accelerates High-Performance, Low-Power Designs
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Cadence Collaborates With Common Platform and Arm to Deliver 45-NM RTL-to-GDSII Reference Flow (Monday Jun. 09, 2008)
Reference Flow Uses CPF-Enabled Cadence Low-Power Solution and Key DFM Technologies for Advanced Node Designs
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STMicroelectronics Announces Certified Design Flow to Accelerate Creation of Next-Generation Silicon (Monday Jun. 09, 2008)
STMicroelectronics today announced the deployment of a certified electronic system level (ESL) System-on-Chip reference design flow.
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Duolog Technologies Pioneers I/O Fabric Generator for Complex SoC Designs (Friday Jun. 06, 2008)
Duolog Technologies announced its new Spinner™ I/O fabric generation tool for automated, bug-free I/O fabric synthesis of complex SoCs.
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Onespin Announces Industry's First SVA Solution for Gap-Free Verification (Thursday Jun. 05, 2008)
Users of OneSpin’s 360 Module Verifier (360 MV) now can employ SVA to implement the GapFreeVerification™ process that slashes verification effort and ensures highest possible verification quality.
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Certess Announces Toshiba's Deployment of its Functional Qualification Solution (Thursday Jun. 05, 2008)
Certess today announced that Toshiba Corporation, Japan's leading semiconductor manufacturer, adopted Certitude, the functional qualification tool, in their recent system-on-a-chip (SoC) for digital TV.
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Berkeley Design Automation Enters Analog/RF Mixed-Signal Verification (Thursday Jun. 05, 2008)
Berkeley Design Automation today announced the availability of true SPICE accurate analog/RF mixed-signal verification based on co-simulation of its award-winning Analog FastSPICE™ circuit simulator with leading Verilog® HDL simulators.
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Bluespec's High-Level Synthesis Toolset is Selected by Mercury Computer Systems for Creation of Next Generation Advanced Computing IP (Wednesday Jun. 04, 2008)
Bluespec today announced that Mercury Computer Systems has adopted Bluespec’s high-level synthesis toolset for creating its next-generation advanced computing IP for FPGAs
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Synopsys Delivers Comprehensive Design Support for TSMC 40-Nanometer Process (Wednesday Jun. 04, 2008)
The two companies also extended the scope of their library distribution agreement to include TSMC's 45-nm and 40-nm Standard Cells, I/Os and Memory Compilers in Synopsys' DesignWare® Library product.
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ARM, Renesas Technology and Synopsys Define Industry's First Low-Power Verification Methodology (Tuesday Jun. 03, 2008)
Synopsys today announced that it has collaborated with ARM and Renesas Technology to define the industry's first methodology to address the rapidly increasing complexity of low power verification.
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Avery Design Realizes Insight For Formal Bug Hunting and Coverage Closure (Monday Jun. 02, 2008)
Avery Design Systems today announced Insight, a new breed of formal analysis tool that delivers a deterministic bug hunting and coverage closure process with unprecedented flexibility and complements today’s SystemVerilog-based intelligent testbench methodologies.
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Synopsys Releases Proven VMM Methodology Standard Library and Applications Under Apache Open Source License (Wednesday May. 28, 2008)
Synopsys' implementation of the VMM methodology, originally defined in the Verification Methodology Manual for SystemVerilog, was recently donated to the Accellera standards organization to speed development of verification interoperability standards.
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LogicVision Introduces Dragonfly Test Platform (Tuesday May. 27, 2008)
Dragonfly delivers a comprehensive hierarchical BIST infrastructure covering memory, logic, and both regular and high-speed device I/Os. The BIST infrastructure is integrated using an advanced design automation tool flow fully compatible with all major EDA flows
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Total solution for standard cell & I/O library, and memory IP characterization by Legend's tools (Tuesday May. 27, 2008)
CharFlo-Cell! is an automatic standard cell & I/O library characterization tool, designed for reliability and manufacturability aware. Traditional tools characterize the cells based on the measurement of pins but without looking into inside-cell for reliability issues such as glitch/metastability.
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Synopsys Unveils New IC Compiler Router Delivering 10X Speed-Up (Tuesday May. 27, 2008)
Driven by leading-edge early users in the microprocessor, consumer, wireless and computer-graphics markets, Zroute has been developed from the ground up to take full advantage of the newest multi-core microprocessor architectures and to solve emerging design-for-manufacturability (DFM) challenges in IC design