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IP / SOC Products News

• MIPS Technologies Strengthens Leadership in Analog/Mixed-Signal IP with Innovative Audio Solution for Multimedia Applications (Monday Feb. 02, 2009)
  MIPS today introduced new Linearized Digital Audio IP for multimedia applications. The new Audio IP provides a high-quality, compact line driving solution for a wide range of applications including DVD players, digital photo frames, set-top boxes and iDTVs.
  
  
• Dolphin Integration today announces the launch of its new range of embedded codecs (Monday Feb. 02, 2009)
  Helium is a family of audio Virtual Components combining the best solutions for low power consumption and Density while offering high audio resolution for portable applications.
  
  
• Virage Logic Extends Comprehensive DDR Interface IP Portfolio with System-Validated DDR3 and New Low Power DDR2 (Monday Feb. 02, 2009)
  Virage Logic today announced two key developments that extend its comprehensive DDR interface IP product portfolio. For high-performance applications, the company's Intelli(TM) DDR3 System Aware IP(TM) solution has been system validated at speeds in excess of 1.6 Gigabits-per-second (Gb/s) on a 65nm process. The Intelli DDR3 memory interface is a complete end-to-end solution including a DRAM memory controller, I/O and the industry's first commercially available all-digital PHY+DLL.
  
  
• Athena Announces the First Cryptography Microprocessor for Embedded and Mobile Applications (Monday Feb. 02, 2009)
  The Athena Group, today announced the introduction of the TeraFire® F5200 cryptography microprocessor. Capable of tackling every mainstream PK cryptography algorithm - from RSA to Suite B - and area optimized for even the most challenging applications, the F5200 is the perfect security solution for embedded and mobile products.
  
  
• Sundance Upgrades Multi-Processor To Storage Interconnect with Single Chip SATA II Solution (Wednesday Jan. 28, 2009)
  Sundance and LogicDesign Solutions today announced the delivery of LogicDesign’s Serial ATA Host and Dual Host Controller IP for the Xilinx Virtex 5 FPGAs featured in the Sundance 7-Series of multiprocessing modules. The LogicDesign core is compliant with the Serial ATA II specification and supports signalling rates of 1.5Gbps SATA-Gen1 and scales to 3Gbps SATA-Gen2. VHDL source code, test benches, validation data and DO-254 documentation can be provided.
  
  
• Evatronix introduces the R8051XC2 to supply SoC designers with the world’s highest performance 8051 8-bit microcontroller IP core (Monday Jan. 26, 2009)
  Evatronix announced today the next generation of its highly successful 8051 configurable IP core – the R8051XC2. Architectural improvements implemented in this release have significantly increased the microcontroller’s performance while other critical factors such as gate count have remained at the same level.
  
  
• Intelop announces TCP-Offload Engine SoC IP with integrated GEMAC, ARP module and AMBA 2.0 bus interface running at 2-Gbps capable of managing thousands of simultaneous TCP sessions (Monday Jan. 26, 2009)
  Intelop Corporation, a leading high end IP developer, customization & electronic engineering design services provider, today announced delivery of their second generation TCP offload engine SoC solution integrated with ARP hardware module, G Bit Ethernet MAC and AMBA 2.0 bus interface running at 2 Gbps sustained rates.
  
  
• Arasan Chip Systems Aligns with SDA on SDXC (Friday Jan. 23, 2009)
  In a continuing effort to develop Arasan’s mobile eco-system, Arasan will be the first IP provider to adopt the SDXC specification from SDA, supporting higher density and faster SD cards. Arasan is in development on the new specification and will be ready to provide a fully compliant solution to the market upon ratification.
  
  
• Mixel and Northwest Logic Partner to Deliver a Complete MIPI IP Solution (Wednesday Jan. 21, 2009)
  Mixel and Northwest Logic today announced the availability of a complete solution for the Mobile Industry Processor Interface (MIPI) Camera Serial Interface-2 (CSI-2). This solution consists of the Mixel MIPI D-PHY (Physical Layer) and the Northwest Logic MIPI CSI-2 Controller Core delivered as silicon Intellectual Property (IP). The companies, working together, provide customers with a complete, low-risk, low-power, low gate-count, full-featured, differentiated MIPI solution.
  
  
• Coreworks Announces Certified BDTI DSP Kernel Benchmarks Results for its SideWorks Architecture (Wednesday Jan. 21, 2009)
  Coreworks today announced certified BDTI DSP Kernel Benchmarks™ results for its Mid-Grain Array Reconfigurable Architecture based upon the SideWorks technology. These results have been obtained for a DSP block, dubbed CWcomp4465, built with a SideWorks data engine tightly coupled with FireWorks™, a simple 32-bit RISC processor, also property of Coreworks.
  
  
• CAST Releases Fastest 8051 IP Core (Wednesday Jan. 21, 2009)
  CAST, Inc. today released a new member of its 8051-compatible processor family, the R8051XC2 IP core. Running 12.1 times faster than the original 8051 chip, the new core is the fastest CAST has offered, and the company believes it to be the fastest 8-bit 8051 IP available anywhere.
  
  
• Synopsys Enhances DesignWare Ethernet IP With Support for IEEE 1588 Specification and ARM AMBA 3 AXI Interface (Tuesday Jan. 20, 2009)
  Synopsys today announced it has enhanced the DesignWare® Ethernet MAC 10/100/1G IP to include support for the latest IEEE 1588 specification as well as an interface to the ARM® AMBA® 3 AXI™ protocol.
  
  
• Lattice Delivers Flexible, Programmable 40 Gbps Serdes Framer Interface, Level 5 (SFI5) IP Core Solution (Tuesday Jan. 20, 2009)
  Lattice today announced the availability of the 40 Gbps SERDES Framer Interface, Level 5 (SFI5) Intellectual Property (IP) Core in the LatticeSC/M FPGA families. The solution utilizes seventeen SERializer/DESerializer (SERDES) channels in the LatticeSC/M devices, including the Lattice SFI5 soft IP core, and enables flexible and high performance next generation 40 Gbps systems.
  
  
• Noesis Technologies releases AWGN channel emulator IP (Friday Jan. 16, 2009)
  Noesis Technologies announced the immediate availability of its standard AWGN Noise Generator IP core (ntAWGN). The core is fully programmable, able to support throughput rates up to 8Gbps, rendering it an ideal solution for channel emulation of high data rate applications.
  
  
• CEVA Introduces Industry's Most Compact and Power-Efficient Single-Core DSP Solution for HD Audio Applications (Thursday Jan. 15, 2009)
  Based on the high-performance 32-bit CEVA-TeakLite-III™ DSP core running at speeds of up to 550MHz, the highly-optimized CEVA-HD-Audio platform is the most compact and power-efficient solution available for HD audio integration into home entertainment and consumer ICs. The CEVA-TeakLite-III DSP core has been adopted by several consumer IC vendors for HD audio applications to date, and is currently being designed into a next generation Blu-ray DVD chip by one of the world's leading DVD IC vendors.
  
  
• IPextreme Teams with Mentor Graphics on 8051 Cores (Tuesday Jan. 13, 2009)
  IPextreme has teamed with Mentor Graphics to offer up its line of 8051 cores for commercial licensing. Originally part of Mentor Graphics’ Inventra™ IP business, the M8051 is a silicon-proven, synthesizable processor core that is binary compatible to 8051 devices and is available in both VHDL and Verilog formats.
  
  
• EyeLytics announces immediate availability of Main Profile HD H.264 Encoder IP core for surveillance market (Monday Jan. 12, 2009)
  EyeLytics today announces the immediate availability of a Main Profile HD H.264 Encoder IP core for the surveillance market. The IP core has been developed for both ASIC and FPGA deployment and has been proven on the Altera Cyclone III Development board. The core logic is optimized for surveillance applications and contains many desirable surveillance features including multi-channel support, constant quality rate control, all intra / inter modes, QPEL, CABAC and low gate count.
  
  
• Symwave and PLDA Demonstrate Worlds First Multi-Vendor USB 3.0 Interoperability (Friday Jan. 09, 2009)
  Symwave and PLDA today announced collaboration on a USB 3.0 interoperability demonstration at CES. The demonstration will showcase real-world data transfers between a PLDA SuperSpeed USB 3.0 host and a Symwave device at 5 Gigabits per second.
  
  
• Imagination Technologies extends graphics IP core family with POWERVR SGX543 (Thursday Jan. 08, 2009)
  Imagination Technologies announces POWERVR SGX543, the first graphics processor IP core based on Imagination’s extended POWERVR Series5XT architecture, which enables higher performance POWERVR SGX cores and multi-processor support.
  
  
• Pico Semiconductor Announces the Availability of GPON IP (Thursday Jan. 08, 2009)
  The IP is a GPON ONT SERDES capable of receiving serial data at the rate of 2.488Gbps and transmitting data at the rate of 1.244Gbps with an unmatched jitter performance. The IP core is capable of operating from 0.9V to 1.35V supply voltages and requires no external components.
  
  
• Imagination Technologies introduces POWERVR FRC270 Frame Rate Conversion IP Core (Thursday Jan. 08, 2009)
  Imagination Technologies announces the availability to lead customers of its new POWERVR FRC270 – the only licensable high-quality and low silicon-area IP core for motion compensated, 240Hz frame rate conversion – which sets a new standard in quality and performance per square millimetre.
  
  
• Xilinx Delivers High Quality of Service Connectivity Solution for Streaming Media Across Ethernet AVB Networks (Thursday Jan. 08, 2009)
  Developed in collaboration with Harman International Industries, the Xilinx(R) Ethernet AVB LogiCORE(TM) intellectual property (IP) core uses cutting-edge programmable technology to easily adapt to changes in the emerging IEEE 802.1 Ethernet AVB standard and support custom features. The first release of the Ethernet AVB LogiCORE IP is immediately available for Xilinx Virtex(R)-5 and Spartan(R)-3A field programmable gate array (FPGA) platforms.
  
  
• Xilinx and Xylon Deliver Flexible, Low-Cost Programmable logiTAP Platform for Embedded GUI System Development (Thursday Jan. 08, 2009)
  The logiTAP platform is a full-featured system on programmable chip (SoPC) solution with a touch screen display that enables rapid, cost-effective development, prototyping, and deployment of graphical human-machine interfaces (HMIs) targeting high-volume electronics applications.
  
  
• Imagination Technologies launches ENSIGMA UCC Series3 architecture and UCCP310 IP platform (Thursday Jan. 08, 2009)
  Imagination Technologies announces ENSIGMA UCC Series3, the third generation of the architecture at the heart of the market leading ENSIGMA UCCP multi-standard programmable communications IP platform family, which delivers leading performance and power in a small silicon area.
  
  
• Synopsys DesignWare Controller and PHY IP for PCI Express Successfully Pass PCI-SIG 2.0 Compliance Testing (Wednesday Jan. 07, 2009)
  Synopsys today announced that its DesignWare® digital controller and PHY IP for the PCI Express® 2.0 technology is the first complete, single-vendor PCI Express 2.0 IP solution to successfully pass the PCI Express 2.0 compliance testing at the PCI-Special Interest Group (PCI-SIG®) workshop held in Taiwan in October 2008.
  
  
• Coreworks' announces Stereo and Multi-Channel Configurable Serial Audio Transceivers targeted for next generation broadcasting and digital TV products (Wednesday Jan. 07, 2009)
  Corework’s family of Configurable Multi-Channel Serial Audio Interfaces supports audio devices from a multitude of IC manufacturers and frees designers from vendor dependence while accelerating time-to-market
  
  
• ARC Launches "Sound-to-Silicon" Audio IP Solutions For Portable, DTV, Home Theater, and PC/Laptop Consumer Products (Wednesday Jan. 07, 2009)
  ARC International (LSE: ARK) today introduced new vertically integrated audio intellectual property (IP) solutions for three major consumer electronics product categories: digital TVs and home theaters, portable media devices, and PC and laptop computers. These “sound-to-silicon” solutions comprise ARC’s industry leading audio enrichment software, low power hardware platform, optimized codecs and related software, and development and mastering tools and services.
  
  
• IP Cores from IPextreme Support Mentor Graphics' Precision Synthesis FPGA Tool (Friday Dec. 19, 2008)
  IPextreme has validated its Multi-CAN Controller, its CJTAG-IEEE1149.7 IP cores and its 32-bit Power Architecture e200, V1 ColdFire, V2 ColdFire, 16-bit CR16CP and 8-bit HCS08 processor cores for use with Mentor Graphics Precision® Synthesis flow.
  
  
• Faraday Offers the Miniaturized Cell Library miniLib in both 90nm and 65nm (Thursday Dec. 18, 2008)
  Faraday today announced the availability of the commercial 90nm and 65nm miniaturized cell libraries, miniLib™, in both standard process (SP) and low leakage (LL). The advantage of miniLib™ is its core area reduction, up to 15% in various cases, and still keeping all the merits of their corresponding generic cell libraries. These two miniLib™ has been silicon proven via many function verification through real chips.
  
  
• Renesas Technology Receives Certification for New IP that Supports the PCI Express 2.0 High-speed Serial Interface Standard (Wednesday Dec. 17, 2008)
  Renesas Technology America today announced the development of a new logical- and physical-layer intellectual property (IP) conforming to PCI Express Base Specification Revision 2.0 (PCI Express 2.0 or PCIe 2.0), the latest version of the widely used serial interface standard. This IP allows data transfers at up to 5.0 gigabits per second (5Gbps) and supports the 65-nm semiconductor process node.