D&R Headline News | Most Popular | SoC News Alerts | |

IP / SOC Products News

• Synopsys USB 2.0 PHY IP for Advanced 40-Nanometer Process First to Pass USB-IF Certification (Wednesday Dec. 17, 2008)
  Synopsys' technology-leading USB 2.0 nanoPHY mixed-signal IP, now available in a native 1.8V architecture, meets the full USB 2.0 specification including 5V short tolerance for 24 hours and 3.3V operation. This architecture helps designers embed the DesignWare USB 2.0 PHY IP into system-on-chips (SoCs) utilizing the most advanced process geometries without compromising performance or long-term reliability.
  
  
• Elliptic Introduces Ellipsys Security Architecture Premier Security Software Solution for Embedded Systems (Wednesday Dec. 17, 2008)
  ESA combines these solutions into an overall framework that provides an efficient and portable software solution for embedded security designs. It offers the flexibility to add hardware offload engines either from Elliptic or through cryptographic cores available in popular processors from Intel, Freescale, AMCC and Raza Microelectronics among others.
  
  
• Arasan Chip Systems First to Provide End-to-End Solution with MIPI D-PHY IP (Tuesday Dec. 16, 2008)
  The Arasan D-PHY is a complete serial communications cell optimized for implementing the physical layer of the MIPI DSI, CSI and UniPro protocol. The Arasan D-PHY IP substantially exceeds the MIPI electrical and performance specification, achieving over 1 Gbps transfer speeds per lane, thus delivering a robust design without sacrificing performance.
  
  
• Alma Technologies Launches a High Performance SPDIF-T SPDIF Transmitter Core (Tuesday Dec. 16, 2008)
  The SPDIF-T core implements the SPDIF digital audio transmitter interface in a compact, high-performance, stand-alone package ideal for digital audio applications. The SPDIF-T core conforms to the ISO/IEC 60958, ISO/IEC 61937, AES/EBU, AES3 and SMPTE 337M standards.
  
  
• Virage Logic Expands Silicon Proven 40-Nanometer Embedded Memory and Logic Library IP Portfolio to Low Power Processes (Tuesday Dec. 16, 2008)
  The expanded SiWare(TM) product portfolio provides semiconductor companies with 40nm physical IP that is designed to enable Systems-on-Chip (SoCs) to run faster, manage power more efficiently, use less area, and achieve higher manufacturing yields.
  
  
• Actel Announces Barco's DO-254 Certifiable ARINC 429 IP Core Targeted to ProASIC3 FPGAs (Monday Dec. 15, 2008)
  Actel's ProASIC3 A3P1000 devices, featuring Barco's BA511 ARINC 429 IP core, were selected for a total of four DO-254 certified implementations in commercial aviation programs, including two at the highest Design Assurance Level (DAL-A), and two at the second highest level (DAL-B).
  
  
• Denali Software Features Comprehensive Toggle-Mode DDR NAND Solutions (Thursday Dec. 11, 2008)
  Denali Software is first to announce its comprehensive support of Toggle-mode DDR NAND memory with complete, end-to-end intellectual property (IP) products that enables quick development of system-on-chip (SoC) designs.
  
  
• Evatronix introduces a SuperSpeed USB Device Controller and Verification IP Solution (Thursday Dec. 11, 2008)
  Evatronix’ USB 3.0 Device Controller is designed to the USB 3.0 specification, which provides for a data throughput of up to 5Gbps. This is over 10 times greater than Hi-Speed USB architecture, reflecting the change that has taken place in the portable device market. With storage values exceeding 1 terabyte, USB is evolving to meet consumers’ needs.
  
  
• Verayo Secures FPGAs with Silicon Signatures (Wednesday Dec. 10, 2008)
  Verayo today announced the availability of its new Soft PUF technology for FPGAs and FPGA-based systems. Soft PUF extracts chip-unique signatures to authenticate the FPGA silicon, the underlying board or system.
  
  
• IPextreme announces availability of Freescale HCS08 microprocessor IP Core (Wednesday Dec. 10, 2008)
  The Freescale HCS08 is a synthesizable, state-of-the-art, high performance and low power 8-bit microprocessor that can be easily integrated into any ASIC or FPGA design. The HCS08 also provides an easy migration path to Freescale’s 32-bit ColdFire architecture.
  
  
• LogicVision and Dolphin Technology Join Forces to Deliver Industry's Most Advanced High-Yield Embedded Memory Solution (Tuesday Dec. 09, 2008)
  LogicVision and Dolphin Technology today announced that Dolphin Technology is offering an integrated high-performance and high-yield embedded memory solution that combines the best-in-class technologies from both companies.
  
  
• CAST Deciphers Security System Design Challenges with New AES Encryption IP (Thursday Dec. 04, 2008)
  CAST, Inc. today announced a new family of AES IP cores that make it easier for designers to include fast hardware encryption in security-sensitive electronic systems.
  
  
• Plurality's 64-Core Accelerator Delivers Market's Highest Performance per Cost, Power and Size (Wednesday Dec. 03, 2008)
  Plurality Ltd. today announced the industry’s first complete silicon Intellectual Property (IP) solution for its HyperCore™ processor, the market’s most powerful, space-saving and energy-efficient 64-core shared-memory processing engine.
  
  
• Silicon Image Introduces 225 MHz HDMI v1.3 PHY IC and Soft Link IP Core for Consumer Electronics Applications (Monday Dec. 01, 2008)
  Silicon Image today announced its 225 MHz HDMI™ version 1.3 PHY solution, consisting of the SiI9204 HDMI v1.3 transmitter PHY semiconductor and companion HDMI v1.3 link layer intellectual property (IP) core.
  
  
• eMemory 0.13um OTP Used in LCD Driver Mass Production at TSMC (Wednesday Nov. 26, 2008)
  eMemory have entered the stage of mass production of 0.13um embedded NVM at tsmc, and of completeness in constructing TSMC 0.13um OTP 1.5V/6V/32V high-voltage platform and 0.13um OTP Fuse availability, providing application for high efficiency small panel LCD driver IC in terms of enhancement of customers’ competitiveness.
  
  
• DE Releases UltraLong FFT IP Cores for Xilinx FPGAs (Tuesday Nov. 25, 2008)
  DE announces the availability for immediate delivery the UltraLong FFT IP Core for Xilinx FPGAs
  
  
• Imagination Technologies extends POWERVR I2P Interlace-to-Progressive scan converter IP core family (Tuesday Nov. 25, 2008)
  These latest versions of Imagination's broadcast quality interlace-to-progressive scan converter technology deliver substantially improved image quality, without silicon area penalty. Both cores are available for licensing from Imagination now and are already in design with Imagination's lead partners.
  
  
• POWERVR SGX540 from Imagination Technologies now in silicon (Tuesday Nov. 25, 2008)
  POWERVR SGX540 typically delivers twice the performance of POWERVR SGX530 while consuming significantly less than double the silicon area or power consumption.
  
  
• Sundance and Dillon Marry Fastest FFT with Fastest Virtex-5 LXT FPGA (Monday Nov. 24, 2008)
  Sundance and Dillon Engineering Merge Signal Processing Expertise and FFT IP to Deliver Benchmark Performance for Embedded Defense, Industrial, Geophysical & Medical Systems
  
  
• Ultra-low power 16-bit microcontroller core consumes less than 40 uA per MIPS. (Friday Nov. 21, 2008)
  Tiempo today announces its new chip, fully operational at first run, that silicon-proves its 16-bit microcontroller core IP – TAM16 – on a CMOS 130 nm general-purpose process. The chip logic has been entirely designed in Tiempo’s innovative asynchronous and delay insensitive technology.
  
  
• POWERVR SGX520, the world’s smallest OpenGL ES 2.0 core achieves Khronos conformance (Thursday Nov. 20, 2008)
  POWERVR SGX520 is the world’s smallest 3D graphics processor solution to achieve OpenGL ES 2.0 conformance - reinforcing POWERVR’s credentials as the leading mobile and embedded graphics acceleration solution. POWERVR SGX520 is less than 2.6mm2 in TSMC 65LP process.
  
  
• Imagination announces latest POWERVR VXE video encoder IP cores (Wednesday Nov. 19, 2008)
  Imagination Technologies announced today the availability of two new IP cores in the POWERVR™ VXE video encoder family. POWERVR VXE251 and VXE280 deliver multi-standard encode at SD and HD resolutions respectively
  
  
• GDA Technologies Ships Configurable USB 3.0 Controller (Tuesday Nov. 18, 2008)
  GDA Technologies announced plans today to ship “Pravega”--its USB 3.0 family of cores consisting of a highly configurable Superspeed device and host controllers that are interoperable with third party USB 3.0 PHY’s running at 5 Gbits/s maximum speeds.
  
  
• Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with the availability of the DB9000AXI for the AMBA 3.0 Interconnect (Tuesday Nov. 18, 2008)
  The DB9000AXI IP Core targets TFT LCD panels with 1 Port of 18-bit digital (6-bits/color) or 24-bit digital (8-bits/color) interface or a 2 Port interface, with each port up to 24-bit digital (8-bits/color). The DB9000AXI, with its 64-bit AXI interface and programmable 2 Port TFT LCD Panel Interface, specifically targets high resolution displays.
  
  
• sRAM generator HAUMEA at 90 nm on DOLPHIN Integration's website (Tuesday Nov. 18, 2008)
  The winning performance mix BCD, Best for Consumption and Density, is heralded by the new sRAM Haumea generator at 90 nm LP process.
  
  
• Wipro-NewLogic delivers WLAN and Bluetooth RF IPs in TSMC 90nm (Monday Nov. 17, 2008)
  Wipro-NewLogic today announced that its Bluetooth 2.1+Enhanced Data Rate RF IP (BOOSTTM RF) and IEEE 802.11a/b/g WLAN RF IP (WiLDTM90 RF) are silicon proven in TSMC 90nm.
  
  
• Faraday Technology and Fresco Logic Partner to Validate SuperSpeed USB PHY (USB 3.0) with SuperSpeed Digital xHCI Host and Device Controller (Friday Nov. 14, 2008)
  Faraday Technology and Fresco Logic today announced a partnership to validate the integration of Faraday's USB 3.0 (SuperSpeed USB) PHY IP (Physical Layer IP) with Fresco Logic's USB 3.0 xHCI Host and Device Controller IP.
  
  
• Microtronix updates Multi-port SDRAM Memory Controller IP Cores to support Stratix III and Arria GX FPGA devices. (Thursday Nov. 13, 2008)
  To improve performance of the Memory Controller IP cores, the internal structure was redesign to improve clock distribution networks and incorporate new architectural features available in Stratix III devices. These design changes improved timing closure and boosted DDR2 memory performance from 333 MHz in a Stratix II to over 400 MHz in a top speed grade Stratix III device.
  
  
• PLDA Announces SuperSpeed USB IP Solutions, Providing Designers With Immediate Ability to Integrate USB 3.0 Host And Device Functionality (Thursday Nov. 13, 2008)
  PLDA today announced the immediate availability of a new line of SuperSpeed USB IP products designed for ASIC and FPGA.
  
  
• Northwest Logic Announces the Immediate Availability of x8 PCI Express 2.0 Solution For Xilinx Virtex-5 FXT FPGA Platform (Saturday Nov. 21, 1998)
  This solution combines Northwest Logic’s full-featured x8 PCI Express 2.0 cores and software to provide a complete, pre-packaged x8 PCI Express 2.0 solution. The solution enables high-performance x8 PCI Express 2.0 designs to be quickly developed for Virtex-5 FXT FPGAs.