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IP / SOC Products News

• Imagination Technologies' Multi-Standard Video Core Passes Allegro H.264 Test Suite (Monday Dec. 18, 2006)
  PowerVR MSVDX IP Shipping Now
  
  
• Sarance Technologies Delivers Interlaken Protocol IP Core for Xilinx Virtex-5 FPGAs (Monday Dec. 18, 2006)
  New IP Core Implements Next Generation High-Speed Serial Chip-To-Chip Packet Interface
  
  
• Denali Launches MLC NAND Flash Solutions for SoC Designs (Monday Dec. 18, 2006)
  Databahn NAND Flash Controller IP and Spectra NAND Flash Management Software Speeds Deployment of MLC NAND Flash Memory in Electronic Products
  
  
• ASIC Architect Announces the Availability of Configurable AMBA3 AXI Bridge for PCI Express Controller Cores (Monday Dec. 18, 2006)
  This solution will enable SoC designers to plug-in PCI Express Controller Core into AMBA3 AXI system bus, and mitigate the implementation risk and time-to-market challenges
  
  
• Jetstream Media Technologies Announces a Full Line of Security IP Cores for ASIC and FPGA (Thursday Dec. 14, 2006)
  The broad product line implements many security standards including AES, AES-CCM, AES-GCM, XEX-AES, secure hashing algorithms, Triple-DES and public key cryptography for applications ranging from secure wireless communication, storage server to network devices.
  
  
• PLDA Announces PCI-SIG Compliant Programmable Switch IP for PCI Express (Thursday Dec. 14, 2006)
  The Programmable Switch IP, which includes an upstream and downstream instance of PLDA's XpressRich shared-silicon IP Controller connected with a glue logic, is a highly configurable solution suitable for connecting x1, x4, and x8 lane components
  
  
• Arasan Announces Support for SDIO Version 2.0 in its SDIO Device IP (Tuesday Dec. 12, 2006)
  Arasan provides a Total Technology Solution to all its licensees including IP source code, a test environment, sample device drivers, synthesis scripts, and complete technical documentation.
  
  
• IPextreme to Bring Expanded Portfolio of Advanced Infineon IP to Rapidly Growing Automotive Electronics Market (Monday Dec. 11, 2006)
  IPextreme will market, license and support Infineon’s MultiCAN, MCDS, MLI and MSC interface blocks to system on chip (SoC) designers seeking to integrate state-of-the-art network, debug, and fast serial interface technology
  
  
• Virage Logic and Tensilica Introduce Core-Optimized IP Kits for Tensilica's Diamond Standard Processors (Monday Dec. 11, 2006)
  Kits are Optimized to Meet Area, Performance and Power Requirements
  
  
• Mentor Graphics Introduces its High-Speed USB-Certified PHY for Embedded Host Applications in the SMIC 0.13 micron Process (Tuesday Dec. 05, 2006)
  This “proven-in-silicon” USB 2.0 PHY implements a UTMI+ Level3 USB Transceiver Macrocell Interface, and offers support for device, host, embedded host and OTG USB controllers
  
  
• Chipidea Achieves Industry's First USB High Speed PHY Certification in TSMC 65nm Technology (Tuesday Dec. 05, 2006)
  Benchmark Assures PHY Quality for Small Area, Low Cost SoC Integration
  
  
• True Circuits Announces New Line of 65nm Timing IP; Customers' Product Shipments Planned for 2007 (Monday Dec. 04, 2006)
  IP Suits High-Speed Timing Applications Requiring Low Jitter, Low Power and Fast Restarts
  
  
• Novelics Introduces Silicon-Proven coolSRAM-1T for SoC Designers with Large Embedded Memory Needs (Monday Dec. 04, 2006)
  A leading provider of multi-standard semiconductor application-specific integrated circuits for Mobile TV and Digital Audio broadcast standards started production ramp up of chips with the Novelics’ embedded coolSRAM-1T
  
  
• Z-RAM Gen2 Ultra-Dense Memory Technology from ISi Significantly Improves Speed and Power (Monday Dec. 04, 2006)
  Z-RAM technologies achieve world-leading density and performance by using a single transistor as a memory bitcell, which is made possible by harnessing the Floating Body Effect found in circuits fabricated using SOI (silicon-on-insulator) wafers.
  
  
• Tensilica Introduces Four Video Processor Engines Including Main Profile H.264 Support (Monday Dec. 04, 2006)
  New Drop-In Diamond Standard Processors for H.264, VC-1/WMV9, MPEG-4 and MPEG-2 Video for SOC Design
  
  
• Tensilica Introduces Xtensa LX2 and Xtensa 7 Configurable Processors (Monday Dec. 04, 2006)
  New Cores Extend Tensilica's Configurable Processor Technology Leadership
  
  
• Low Power Hard Core Diamond Standard Processor for TSMC 0.18-micron Technology Available Through Global Unichip (Monday Dec. 04, 2006)
  First Hardened Diamond Standard Processor Available; Reduces SOC Integration Cost
  
  
• Arasan Announces Support for Part A2 of the SDIO Version 2.0 Specification (Friday Dec. 01, 2006)
  The Part A2 enhancement extends the basic DMA Part A1 capability to an advanced Scatter-gather method. The new method improves the performance allowing transfer to/from multiple memory locations in a single DMA transaction.
  
  
• Chips&Media's BodaHx5 Multi Standard HD (High Definition) decoder IP solution provides customers with superior features and high quality video for mobile and home appliance market (Thursday Nov. 30, 2006)
  The new BodaHx5 multi-standard HD decoder IP solution offers an impressive array of video features including support for MPEG-2 MP@HL / H.264 HP@L4.1 /VC-1 AP@L3.0 video decoding at 30fps while only running at 133MHz internal clock frequency
  
  
• Evatronix Partners with JMicron to Deliver Total USB Solutions (Wednesday Nov. 29, 2006)
  Silicon-proven USB controller IP cores and PHYs available for multiple CMOS processes
  
  
• IP Cores, Inc. Announces New High-Speed IP Combo XEX-AES Family of Cores Supporting New IEEE P1619 Draft Standard (Wednesday Nov. 29, 2006)
  IP Cores, Inc. announces a family of silicon IP cores supporting new IEEE P1619 standard draft. Starting from 30K ASIC gates and delivering up to 70 Gbps throughput, XEX3 cores provide a compact and flexible solution for an SoC designer working on a secure storage solution.
  
  
• Chipidea Offers the Industry's Most Advanced Portfolio of AFE and Data Converter IP in IBM, Chartered and Samsung processes (Wednesday Nov. 29, 2006)
  The data converter IP was prepared on Chartered’s 90nm and 65nm technologies, part of the IBM-Samsung-Chartered Common Platform. Chipidea’s IP solutions provide SoC builders with greater flexibility to integrate data converter IP into their designs, and heralds Chipidea’s readiness to supply complete analog front-end IP in advanced technology.
  
  
• Intrinsix Announces Availability of Tri-Mode Television IF Subsystem IP (Tuesday Nov. 28, 2006)
  The Tri-Mode Television IF Subsystem IP (TMTVIF), which has an Intrinsix SDM Analog to Digital Converter (ADC) at it's core, is designed to support tuners for the two major television standards worldwide: Traditional, with a High Intermediate Frequency (IF); Direct Conversion, via the Zero IF mode; as well as a third option, a Low IF mode.
  
  
• TurboConcept's WiMAX Turbo Code IP Core for LatticeSC FPGA Devices (Monday Nov. 27, 2006)
  This IP core supports all modes of the IEEE 802.16 CTC standard, including Orthogonal Frequency Division Multiplexing (OFDM) PHY and Orthogonal Frequency Division Multiple Access (OFDMA) PHY. Available in three speed versions, the typical throughput in a LatticeSC device can exceed 80 Mbits (at 5 iterations).
  
  
• IP Cores, Inc. Announces New Multi-Gigabit IP Combo AES/XEX and AES/GCM Core Supporting New IEEE P1619 Draft Standard (Thursday Nov. 23, 2006)
  IP Cores, Inc. announces silicon IP core supporting new industry standards. Starting at 60K ASIC gates and delivering up to 10 Gbps throughput, GXM3 cores provides a compact and efficient solution for an SoC designer working on a secure IEEE P1619 storage or IEEE 802.1AE networking solution.
  
  
• IPextreme to Accelerate Broad Adoption of Nexus 5001 Debug Standard by Making Freescale Interface Blocks Widely Available (Monday Nov. 20, 2006)
  IPextreme will market, license and support Freescale’s Nexus 5001 interface blocks to drive broad adoption of the Nexus standard targeting automotive, mass-storage, avionics and communications applications.
  
  
• Wipro-NewLogic announces Dual Role Device MAC IP Core based on Certified Wireless USB Technology (Monday Nov. 20, 2006)
  Wipro-NewLogic’s Dual Role Device MAC IP Core can work in Limited Host mode, Device mode or simultaneous Limited Host and Device mode. It can thus be implemented as either a Device or a Dual Role Device. It is designed keeping early silicon success in mind and is optimized for performance.
  
  
• MOSAID Introduces SRAM IP with Industry's Lowest Leakage - Broad IP Platform Enables Fast, Low-Power, Low-Leakage Designs (Monday Nov. 20, 2006)
  MOSAID Technologies, a Gartner-rated top-10 silicon IP (intellectual property) supplier, today expanded the award-winning MOSAID Mobilize(TM) product family with single port and dual port SRAM compilers for leading 90nm foundries. The compilers produce SRAMs with power consumption up to eight times lower than any generic CMOS semiconductor IP in the industry.
  
  
• Mixel Announces First Silicon-Proven Mobile Display Digital Interface Transceiver IP for Digital Handsets (Monday Nov. 20, 2006)
  The MDDI is a High Speed Serial Interface That Offers Lower Power Consumption and Reduces Number of Wires Required to Connect Digital Controller to LCD
  
  
• Faraday Introduces 533 MHz Embedded RISC CPU Core FA626 Using UMC 0.13 um Process (Monday Nov. 20, 2006)
  Breakthrough in performance of ARM-Architecture CPU core meets various market requirements