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IP / SOC Products Articles

• H.264 High Profile: Codec for Broadcast & Professional Video Application (May. 20, 2010)
  High definition video content is becoming rampant as more and more countries are now transitioning into digital life. The ways to deliverHigh definition content in a bandwidth limited channel have become challenge in itself. To cater to such highly demanding broadcast & professional video markets, we require a compression / decompression standard that allows no compromise on the quality of the video that has to be broadcasted over a bandwidth constrained networks.
  
  
• Stochastic Computation applied to the design of Error Correcting Decoders (Nov. 05, 2009)
  We describe the application of stochastic computation to a family of error-correcting decoders. We have applied this technology to the Low Density Parity Check (LDPC) codes first described by Gallagher in the 1960s. LDPC is the highest performance error correcting code known to date and is used in IEEE standards including WiFi, WiMAX, DVB-S2, and 10 GbE.
  
  
• Femtocells Gather Momentum - Security Design is Pivotal to Consumer Acceptance (Nov. 02, 2009)
  AT&T customers in Charlotte, North Carolina have the good fortune of being the latest subscribers that are can now able to sign-up for a femtocell which offers consumers reliable, high-bandwidth mobile services at home. A femtocell is a miniaturized version of a cell site that a customer installs at home and connects to a DSL or cable modem. This article offers background on how femtocell networks are constructed, offers a snapshot on standardization and interoperability efforts and then digs in to the important security requirements that are vital to successful deployment of femtocells.
  
  
• A Set of VHDL IPs to Evaluate Performance of Netwoks-on-Chip (Oct. 19, 2009)
  The design of a Network-on-Chip – NoC requires the use of simulation tools to characterize its performance metrics. However, cycle-accurate models are time-costly and the simulation of a large system can consume several hours of computing. The evaluation time can be significantly reduced by running the performance evaluation experiments on a NoC implemented directly on hardware, typically using FPGA.
  
  
• Customizable SoC SPEAr from STMicroelectronics Solving Time to Market Issues (Oct. 05, 2009)
  Some of the most common known issues any equipment manufacturer needs to solve are Time To Market and Time To Volume strong constraints. These issues are also linked with an increased fragmentation of the final products portfolio to be offered, even if often these products are using the same kernel of basic SoC product. SPEAr concept is one of the most suitable versatile but standard SoC for a customer to solve these issues
  
  
• A 24 Processors System on Chip FPGA Design with Network on Chip (Sep. 21, 2009)
  In this paper we present a single FPGA chip implementation of a NOC based shared memory multiprocessor system with 24 processors connected to a main memory composed of 4 DDR2 banks. All the processors and DDR2 memories are connected to a NOC through Open Core Protocol (OCP-IP) interface. The MPSOC have been validated and evaluated through actual execution with matrix multiplication application. A Global Asynchronous Local Synchronous (GALS) design methodology have been adopted throughout the design cycle and exploited for clock trees designs.
  
  
• OTP with a ROM Conversion Option Provides Flexibility and Cost Savings for On-Chip Microcode Storage (Aug. 31, 2009)
  This article covers the flexibility that an OTP with ROM option provides with regard to the product life cycle of high volume products. You will learn how to estimate OTP programming cost and make trade-off analysis to help you decide whether or not a mask ROM conversion makes economical sense.
  
  
• Picking the right MPSoC-based video architecture: Part 4 (Aug. 20, 2009)
  A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 4: Application-driven architecture design.
  
  
• Picking the right MPSoC-based video architecture: Part 3 (Aug. 20, 2009)
  A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 3: Critical communication bus structures
  
  
• Picking the right MPSoC-based video architecture: Part 2 (Aug. 18, 2009)
  A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 2: CPU configurations and interconnections.
  
  
• Picking the right MPSoC-based video architecture: Part 1 (Aug. 18, 2009)
  A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing
  
  
• Embedded Instrumentation Integration Using IEEE Nexus 5001 and 1149.7 (Aug. 13, 2009)
  New capabilities for improving embedded control and visibility for chip level analysis and design for debug logic and interfaces to an IC are needed to enable real time functional control, test, and observation of embedded and otherwise not easily accessible operational features. IEEE 5001, also known as Nexus provides a standard method and architecture for embedded instrument interfaces. New debug and instrumentation capabilities, being introduced by Nexus working groups, include support for IEEE 1149.7, which defines the next generation for (JTAG) Debug and Test Control.
  
  
• A Cost-Optimized Set-Top Box Architecture (Aug. 10, 2009)
  This paper presents a cost-optimized system on chip architecture for cable-based high definition TV set-top box platforms with integrated DOCSIS channel bonding and high speed home networking.
  
  
• IP-based Toolbox for Digital Signal Processing Reuse: Application to Real-time Spike Sorting (Jul. 06, 2009)
  The design flow of digital signal processing has to be improved. In a specific application, we propose a definition of the IP content and the structure of an IP-based toolbox. The case study consists in an clustering algorithm for spike sorting.
  
  
• Modelling OCP Interfaces in SystemC: Standards built on top of OSCI's TLM-2 (Jul. 06, 2009)
  This paper describes the approach adopted by OCP-IP to providing SystemC modelling interfaces for a real memory-mapped bus family. TLM-2.0 has shown itself to be an effective and efficient base technology for all variants of OCP at all levels of abstraction, from cycleaccurate to untimed.
  
  
• SuperSpeed USB 3.0: Ubiquitous Interconnect for Next Generation Consumer Applications (Jun. 22, 2009)
  To address the bandwidth limitations of the USB 2.0 interface, the USB Implementers Forum (USB-IF) released the SuperSpeed USB 3.0 specifications in November 2008. The USB 3.0 specification provides a maximum bandwidth of up to 5Gbps while limiting power consumption. In this white paper we present the features of the USB 3.0 protocol, discuss the new usage models it enables and compare it with some of the existing interface standards popular in the market today.
  
  
• Networks-on-Chip with Reprogrammable Interconnections (Jun. 11, 2009)
  One of ways for enlargement of ASIC based Systems-on-chip field of application is using of internal interconnection system based on reconfigurable Network-on-chip. In this article we suggest some variants of reconfigurable system-on-chip structure based on physical and virtual channels, evaluate their parameters. We suggest mathematical model for relative hardware cost of systems evaluation We compare hardware cost and throughput for these variants of systems.
  
  
• Tailored SoC Building Using Reconfigurable IP Blocks (Jun. 08, 2009)
  Increasing complexity, faster changing standards and shorter time to market ask for composing systems out of standard IP components. An example shows the construction of a System-on-Chip (SoC) based on standard IP components for a Digital Audio Broadcasting consumer application.
  
  
• Can MIPI and MDDI Co-Exist? (Jun. 08, 2009)
  Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?
  
  
• Adopting An SOC-based Approach to Designing Handheld Medical Devices (May. 28, 2009)
  The rapid growth of the medical devices industry has seen a comparable increase in demand for handheld medical devices, from personal defibulators to continuous glucose monitors. Designing such devices can be a daunting task.
  
  
• A Re-Usable Level 2 Cache Architecture (May. 25, 2009)
  This paper presents the architecture of a high performance level 2 cache capable of use with a large class of embedded RISC cpu cores. The cache has a number of novel features including advanced support for data prefetch, coherency, and performance monitoring. Results are presented showing the performance improvement profile over a large class of applications.
  
  
• New Applications Areas Driving Higher Dynamic Range Converters (May. 18, 2009)
  With the advent of higher broadband speeds in the fixed line and wireless systems, the need for higher performing data converters has become apparent. In this article, we discuss the different standards that are pushing this trend and how single tone testing, in some cases, does not accurately determine the performance in communication systems.
  
  
• USB OTG: The only wired interface portable consumer products need? (Apr. 23, 2009)
  With so many portable product interfaces, UBS On-the-Go is perhaps the best choice in many situations
  
  
• Practical Design and Implementation of a Configurable DDR2 PHY (Apr. 20, 2009)
  To reduce the hassles presented to SoC designers by the DDR2 interface, many problems have been resolved by DDR2 PHY IP development. A DDR2 high speed PHY block is almost always developed as a full custom mixed signal design. There are many good reasons for implementing a full custom design, where every cell and every signal route is fully controlled. Such pre-defined, hard designs offer a way to deal with the tight timing budget of DDR2, which is in the range of a few tens of picoseconds. Another reason is the physical dimensions in which this block must fit. This paper presents through examples of the methods selected while performing physical implementation of the IP.
  
  
• Inside Ceva's high-performance XC core for 4G handsets, infrastructure (Apr. 16, 2009)
  In February CEVA announced a new family of high-performance licensable DSP cores, the CEVA-XC family, targeting 4G cellular applications, including LTE and WiMax -- for both handsets and infrastructure. BDTI went inside and took a look at the company's performance and features claims.
  
  
• Using an interface wrapper module to simplify implementing PCIe on FPGAs (Apr. 09, 2009)
  Stephane Hauradou compares various approaches to implementing PCI Express on FPGAs to the PLDA EZDMA module interface wrapper to provide a simple and robust user interface with PCI Express hard IP.
  
  
• Building advanced Cortex-M3 applications (Apr. 09, 2009)
  The ARM Cortex-M3 architecture provides many improvements compared with its predecessor, the popular ARM7/9, and is designed to be particularly suitable for cost-sensitive embedded applications that require deterministic system behavior. This article describes how developers can best utilize the advanced capabilities of the Cortex-M3 when designing embedded applications.
  
  
• SoC IP Interfaces and Infrastructure -- A Hybrid Approach (Apr. 06, 2009)
  This paper presents three generations of SoC designs beginning with a flat single AHB Bus based interconnect, followed by a multi-tier AHB/APB segmented communication infrastructure and finally our hybrid approach using both the AHB bus for control path operations and point to point BVCI connections through an internal crossbar for data flow. This architecture eliminates many of the dataflow bottlenecks common to SoCs and leaves the device constrained only by processing power and DRAM bandwidth. The power benefits of the architecture are also discussed throughout.
  
  
• Optimization of current-limiting solutions for USB 3.0 (Apr. 06, 2009)
  In addition to transfer speed enhancement in USB 3.0, the requirement for power supply is also increased to meet various peripheral demands. The article introduces the Polymeric Positive Temperature Coefficient (PPTC) device, which is an over-current protection device often used in the industry, and compares it with low-voltage solid-state switch for USB 3.0 applications.
  
  
• M-LVDS for true multipoint interfaces on busses--and more (Mar. 30, 2009)
  Multipoint, low-voltage differential signaling (M-LVDS) is an interface standard similar to LVDS. It provides the benefits of high-speed, low-power, and low-EMI transmission solutions to today's bus applications. M-LVDS is suitable for data, control, synchronization and clock signals.