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IP / SOC Products Articles

• Data Over Sound: Encryption is Key (Oct. 28, 2019)
  You can send data over audio and it just might be more secure than using RF.
  
  
• Designing AI enabled System with SOTIF (Safety Of The Intended Functionality) (Oct. 21, 2019)
  Autonomous Vehicles (AV) needs more intelligence when it is on the move. The intelligence is not just an algorithm driven based on multiple sensor inputs alone, but here the intelligence need to be highly situational aware and by keeping the current vehicle dynamics. This needs lot situational and scenario based complex computation and communication with multiple Electronic Control Unit (ECU) within the vehicle.
  
  
• PUF: A Crucial Technology for AI and IoT (Oct. 14, 2019)
  One of the key challenges for AIoT is the protection of AI assets. AI functions often need to detect, evaluate and respond in real time. As a result, a critical security concern is the fact that internal databases and interfaces for AI are not suitable for encryption because such an operation would demand too much time and resources.
  
  
• IP Security Assurance Standard (Oct. 03, 2019)
  This paper introduces an emerging new standard called IP Security Assurance (IPSA) to address these concerns in a manner that is low-overhead, non-disruptive, and scalable across IP families. The standard specifies an approach to highlight IP assets and associated entries in the Common IP Security Concerns Enumeration (CIPSCE) knowledge base for the mitigation implementer to address.
  
  
• Implementing Secure Boot in Your Next Design (Sep. 30, 2019)
  The number of new viruses and malwares created every day is getting close to 1 million. Thus, in an always more connected world, getting protected against these attacks becomes absolutely critical. To make a device trustable one needs to make sure it runs only genuine firmware.
  
  
• How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity (Sep. 26, 2019)
  An FPGA-based SmartNIC employs the expanded hardware programmability of FPGAs to build any data-plane functions required by the tasks offloaded to the SmartNIC. Because FPGAs are reprogrammable, the data-plane functions implemented by the FPGA can be torn down and reconfigured at will and in real time. All such offloaded functions operate at hardware – not software – speeds.
  
  
• The Age of the Monster Chip (Sep. 18, 2019)
  What are the system designs that require a leap in SoC complexity? It's not only big datacenter artificial intelligence (AI) chips, but also autonomous vehicles such as cars, trucks and drones; they are self-landing, reusable rockets; they are medical devices carrying out remote diagnostics.
  
  
• The Gatekeeper of a Successful Design is the Interconnect (Sep. 03, 2019)
  An effective interconnect makes delivering a complex SoC easier, more predictable, and less costly.
  
  
• Re-Architecting SoCs for the AI Era (Aug. 26, 2019)
  This paper will define AI, describe its applications, the problems it presents, and how designers can address those problems through new and holistic approaches to SoC and network on chip (NoC) design. It also describes challenges implementing AI functionality in automotive SoCs with ISO 26262 functional safety requirements.
  
  
• Time Sensitive Networking: An Introduction to TSN (Jul. 29, 2019)
  In the future, Industry 4.0 applications will require increasingly more consistent Ethernet networks. Such networks can only be produced at great cost with the traditional structure. Time-Sensitive networking (TSN) provides a solution aiming to change these current conditions.
  
  
• Configure, Confirm, Ship: Build Secure Processor-Based Systems with Faster Time-to-Market (Jul. 29, 2019)
  Security is a first-order design requirement for processor-based systems. Processor designers implement security functionality directly into the hardware itself to protect the system at its most fundamental layer.
  
  
• How to use snakes to speed up software without slowing down the time-to-market? (Jul. 22, 2019)
  At BitSim, we have a way to simplify and speed up the development cycle. In this document, we will discuss the issue of network load in an IoT environment as well as "our" way to speed up the development.
  
  
• NVMe/TCP Improves Data Storage (Jul. 01, 2019)
  Adding TCP lets the NVMe protocol for solid-state drives operate SSDs anywhere while appearing as local drives.
  
  
• Testing Of Repairable Embedded Memories in SoC: Approach and Challenges (Jun. 17, 2019)
  This article focuses on how to test repairable memories when we include the repair feature, and it will also look at how it will be affected during Automatic Test Pattern Generation (ATPG) or built-in pattern generation. In addition, it focuses on the common challenges and includes a comparative case study on enabling and disabling BIRA features in memories.
  
  
• SoC Interconnect: Don't DIY! (Jun. 13, 2019)
  With so many acquisitions in the interconnect IP market, you might be forgiven for thinking DIY interconnect is a good idea.
  
  
• Dual Mode C-PHY/D-PHY: Enabling Next Generation of VR Displays (May. 28, 2019)
  For many years, Virtual Reality (VR) and Augmented Reality (AR) were strongly linked to gaming and entertainment applications. Today, the VR/AR and their combined version, Mixed Reality (MR), have their applications extended to other domains like healthcare, military, education, manufacturing, retail, marketing and advertising. What are the challenges for next generation VR displays? What makes the MIPI interfaces the best fit for VR/AR/MR applications?
  
  
• Enabling Composable Platforms with On-Chip PCIe Switching, PCIe-over-Cable (May. 28, 2019)
  A number of interconnect protocols have emerged (NVMe-oF, CCIX, Gen-Z, CXL) promising to address the challenges introduced by the composability model. While these interconnect technologies mature and make their way towards mainstream adoption, system vendors still have various options that leverage the well established PCI Express protocol to enable scale-up and scale-out composable fabrics.
  
  
• Distorted Waveform Phenomena in 7nm Technology Node and its Impact on Signoff Timing Analysis (May. 06, 2019)
  In today’s deep sub-micron technology nodes like 16nm, 7nm & beyond, there is a huge challenge for accurate static timing calculation. Ever increasing routing congestion, thin metal layers and moreover very high speed signal propagation make these nodes prone to significant crosstalk effects.
  
  
• Image Processing - RTL Implementation of Median Filtering for Image Denoising (Apr. 25, 2019)
  This article explains step by step implementation of Median Filtering Algorithm in Verilog. This filtering technique is then applied to noisy image for denoising. This article also explains simple Verilog based testbench and Matlab scripts for image pre/post processing operation for verifying the same.
  
  
• Integrated ADAS Domain Controller SoCs with ISO 26262 Certified IP (Apr. 22, 2019)
  This article highlights the new integrated automotive ADAS domain controller SoC architecture, and describes how designers can accelerate their SoC-level certification and time-to-production with automotive-certified IP.
  
  
• Memory Testing - An Insight into Algorithms and Self Repair Mechanism (Apr. 08, 2019)
  Conventional DFT methods do not provide a complete solution to the requirement of testing memory faults and its self-repair capabilities. A promising solution to this dilemma is Memory BIST (Built-in Self-test) which adds test and repair circuitry to the memory itself and provides an acceptable yield. This article seeks to educate the readers on the MBIST architecture, various memory fault models, their testing through algorithms, and memory self-repair mechanism.
  
  
• Signoff Iteration Reduction Technique for Fixing Top Level Antenna (Apr. 01, 2019)
  While developing large-sized chips, “divide & conquer” techniques are used. This involves partitioning the design, implementing each block individually, and stitching them together at the top level. Even if the blocks are all clean with respect to physical and timing signoff, they show incremental violations when they are stitched together.
  
  
• A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology (Mar. 25, 2019)
  The intent of this paper is to explain the varied kinds of DRCs (Design Rule Checks) that are encountered in the Physical Design flow. This paper will discuss the Metal DRC violations (7nm Technology) generally seen at the block level and outline the practical approach to fix them.
  
  
• Guide to Choosing the Best DC-to-DC Converter for Your Application (Mar. 25, 2019)
  This white paper introduces a procedure for choosing the proper DC-DC switching converter for a given application. It explains basic, performance, and optional metrics in detail. It also demonstrates other practical aspects that are sometimes overlooked by system designers. Multiple application examples are provided.
  
  
• Which DDR SDRAM Memory to Use and When (Mar. 18, 2019)
  This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
  
  
• Integration of power:communication interfaces in smart true wireless headset designs (Mar. 13, 2019)
  True Wireless Headsets (TWS headsets) attract attention thanks to better battery life, features, design and price points, but to be smart and user friendly, these devices require efficient data exchange between the charger cradle and earbuds.
  
  
• Reducing DFT Footprints: A Case in Consumer SoC (Mar. 11, 2019)
  Nowadays, placing multiple IPs on a single chip plays the most vital role in satisfying System on Chip ASIC specification requirements. Most of the time, these different IPs will have different clock domains.
  
  
• Hidden Signals: The Memories and Interfaces Enabling IoT, 5G, and AI (Mar. 11, 2019)
  This IDC Technology Spotlight Report, sponsored by Rambus, highlights key, often hidden, memory and interface technologies that are enabling high performance electronic systems to serve the disruptive trends of the next decade like IoT, 5G, and Artificial Intelligence.
  
  
• SOC Stability in a Small Package (Mar. 11, 2019)
  There are some IPs in SOC which are of general use and malfunction on them impacts a entire SOC. We Identified these IPs and analyze impact on SOC due to their malfunction.
  
  
• PCIe 5.0 vs. Emerging Protocol Standards - Will PCIe 5.0 Become Ubiquitous in Tomorrow's SoCs? (Mar. 04, 2019)
  Over the last 3 years, a number of protocol standards have emerged, aiming to address the growing demand for higher data throughput and more efficient data movement. While CCIX, Gen-Z, and OpenCAPI are relative newcomers, PCIe has been around for almost 2 decades. With the imminent release of version 5.0 of the PCIe Specification, SoC designers have a variety of options for supporting bandwidths in excess of 400 Gbit/s while improving overall communication efficiency.