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IP / SOC Products Articles

• Right-Sizing Your Cryptographic Processing Solution (Mar. 04, 2019)
  In this white paper we investigate different cryptography implementation options and trade-offs, describe the measurable parameters, and analyze examples. We introduce and use the new EEMBC SecureMark™ benchmark for these measurements
  
  
• Guide to Choosing the Best LDO for Your Application (Feb. 18, 2019)
  To know which LDO you need, you must first define the application of your LDO and then examine which parameters are most important when dealing with that application. With the multiple parameters that characterize a particular LDO, it is not easy to determine which LDO is best suited. To help you figure this out, we have put together this reference. This guide presents a list of all the key LDO parameters along with their definitions, the most common applications of LDOs, and which parameters are critical for each.
  
  
• Creating a custom processor with RISC-V (Feb. 18, 2019)
  The RISC-V instruction set architecture is an open framework that allows design of a customized processor that can leverage tools and software libraries created for the standard versions.
  
  
• Transitioning from DDR4 to DDR5 DIMM Buffer Chipsets (Feb. 07, 2019)
  There are a number of key changes to DDR that introduce new design challenges. However, savvy designers will use the transition time to nail down solutions.
  
  
• What can GPUs bring to ADAS? (Feb. 07, 2019)
  One of the most talked about topics in the automotive industry today is advanced driver assistance systems (ADAS). These systems assist the driver in dealing with potential issues in a number of ways.
  
  
• Achieving Groundbreaking Performance with a Digital PLL (Feb. 04, 2019)
  This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.
  
  
• The Four Characteristics of an Optimal Inferencing Engine (Jan. 31, 2019)
  Advice on how to compare inferencing alternatives and the characteristics of an optimal inferencing engine.
  
  
• The Tradeoffs of Low Dropout (LDO) Voltage Regulator Architectures and the Advantages of "Capless" LDOs (Jan. 28, 2019)
  Power management of battery-powered electronic devices is becoming increasingly more important for the microelectronics industry. This white paper details the difference between low dropout (LDO) voltage regulators that use external output capacitors and those that do not, and how your system designs can benefit from not using an output capacitor. Well-designed capless LDO voltage regulators can have multiple benefits, and they are presented here.
  
  
• Secure SOC for Security Aware Applications (Jan. 14, 2019)
  Security is a two-way sword, increasing the security makes user difficult to access the chip and increasing user access increases chances for the chip to be hacked.
  
  
• Bulletproofing PCIe-based SoCs with Advanced Reliability, Availability, Serviceability (RAS) Mechanisms (Dec. 19, 2018)
  We start this article by defining “RAS” in the context of PCIe interfacing and looking at the provisions for RAS mechanisms in the PCIe Specification. We then explore some potential PCIe hazards SoC designers can face and the RAS mechanisms that can be implemented to detect, recover, or prevent these hazards. We conclude with recommendations for choosing a PCIe silicon IP solution that helps mitigate these risks.
  
  
• Extending 8K over a single, cost-effective wire with TICO lightweight compression (Dec. 13, 2018)
  With HD omnipresent and 4K seemingly still in its early stages, an even higher resolution, namely 8K (or UHDTV2) is arising. Display and projection manufacturers are already presenting their first 8K-capable products and the 2018 Winter Olympics were partly filmed in this currently largest video resolution format. Taking a peek into the future, Japan’s national TV “NHK” has even announced to broadcast the full Olympic games on home turf in 2020 in glorious 8K.
  
  
• PCI Express 3.0 needs reliable timing design (Dec. 03, 2018)
  PCI Express (PCIe) is an important standard for chip-to-chip communications and serves as a standard for connecting motherboards to peripheral cards. It can be challenging, however, to implement the reference clock so that it meets the various requirements of the PCIe standard.
  
  
• Designing an Effective Traffic Management System Through Vehicle Classification and Counting Techniques (Nov. 29, 2018)
  This white paper proposes an effective approach for moving vehicle classification followed up by vehicle counting, for classified types of vehicles. This data helps in strategic city planning, and in generating meaningful insights for improving efficiency and reliability in Traffic Management.
  
  
• Improving reliability of non-volatile memory systems (Nov. 19, 2018)
  Complex systems like Advanced Driver-Assistance Systems (ADAS), medical, and industrial applications need to be reliable, secure, and safe. In these systems, firmware and associated data are stored in Non-Volatile Memory (NVM) because code and data must be retained when power is not being supplied. Thus, NVM plays a crucial role in system reliability.
  
  
• Gen-Z Primer for Early Adopters (Nov. 12, 2018)
  In this article we look at the Gen-Z fabric as a solution to eliminate existing system bottlenecks and significantly improve system efficiency and performance by unifying communication paths and simplifying software using the CPU-memory load/store language throughout.
  
  
• Auto OEMs, Tier-Ones: Think SoC Designs (Oct. 09, 2018)
  Automotive OEMs and Tier-1 suppliers are in a unique situation these days. Game-changing technology undertakings and hyper business growth in advanced driver assistance systems (ADAS) and autonomous cars are turning automotive design platforms upside-down.
  
  
• New Power Management IP Solution Can Dramatically Increase SoC Energy Efficiency (Oct. 01, 2018)
  This Position Paper describes a family of Power Management IP solutions integrated by Dolphin Integration’s customers into their SoC to drastically improve Energy Efficiency (EE). SoC performance metric is changing, moving from pure performance metric (GHz or MIPS) to performance efficiency and minimum power consumption. This new metric, already crucial for IoT or mobile devices, is becoming key in various applications, like automotive, embedded or space.
  
  
• CPU Soft IP for FPGAs Delivers HDL Optimization and Supply Chain Integrity (Sep. 27, 2018)
  RISC-V open ISA can help military and aerospace designers who are facing challenges of minimizing power consumption, BOM cost and board area by allowing the optimization of the instruction set to give the most efficient implementation for each specific application.
  
  
• Optimizing AI and Machine Learning with eFPGAs (Aug. 31, 2018)
  Why the performance and flexibility offered by eFPGA is turning out to be a game changer for anyone designing AI and machine learning and struggling to meet the compute demands.
  
  
• Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product (Aug. 20, 2018)
  This paper explains the changes in the role of the semiconductor industry in the automotive supply chain and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.
  
  
• Why Isn't 56 Gbps Impossible? (Aug. 16, 2018)
  How fast can you force data through a pair of wires? It is a trick question, of course. The answer depends on the wires, the material and geometry around them, the distance, and your choice of transceiver technology.
  
  
• 4K Video over IP workflows (Jul. 16, 2018)
  Considering the necessary bandwidth for the next generation of television with UHDTV resolutions and higher frame rates, live uncompressed transport across 10GB Ethernet network or existing SDI infrastructure is not possible anymore. In fact, uncompressed 4K video at 60fps 4:2:2 requires 12Gbps or more for 4:4:4.
  
  
• Sharing NVMe SSDs for heterogeneous architectures (Jul. 09, 2018)
  New computing applications, such as big data analytics and deep learning, need very optimized and well balanced computing, networking and storage resources. After being developed on CPU-centric architectures, it is now going on heterogeneous architectures by using computing accelerators like FPGAs and GPUs.
  
  
• Convey UHD 4K Video over 1Gbit Ethernet with the intoPIX JPEG 2000 "Ultra Low Latency" compression profile (Jul. 02, 2018)
  Considering the uncompressed bandwidth of a UHD 4K video stream in 4:2:2 or 4:4:4 and the massive amount of deployed Gigabit Ethernet infrastructures, a codec that can offer the same benefits in terms of quality, latency and reliability as uncompressed transport, with a sufficient compression ratio to go under 1Gbit/second, is a key advantage.
  
  
• How embedded FPGAs fit AI applications (Jun. 18, 2018)
  Artificial intelligence, and machine learning in particular, is reshaping the way the world works, opening up countless opportunities in industry and commerce, but the optimum hardware architecture to support neural network evolution, diversity, training and inferencing is not determined. Alok Sanghavi surveys the landscape and makes the case for embedded FPGAs.
  
  
• NVMe host IP for computing accelerator (May. 29, 2018)
  NVM Express (NVMe) SSDs are well adopted by the storage industry. It delivers high performances in term of IOPS, throughput and latency. It comes with a various range of capacity and form factors including PCIe Add-In-Card, 2.5" U.2, M.2 and recently as a single BGA chip.
  
  
• Considerations Regarding Benchmarking eFPGAs (Embedded FPGAs) (May. 22, 2018)
  There are many things to consider, but if you choose the right solution for your particular application, you will be able to unlock the full potential of your eFPGA.
  
  
• Multi-Channel Multi-Rate (MCMR) Forward Error Correction (FEC) - IP for High Speed Networking Applications (May. 21, 2018)
  The need for higher and higher bandwidth is growing, which is pushing the SerDes speed to 56G and beyond. The next generation of networking devices are already pushing for 400G bandwidth and above. Both the OIF CEI-56G and IEEE working groups have ratified the 56G specifications, and for higher speed SerDes, PAM4 signaling is the way forward.
  
  
• Demystifying MIPI C-PHY / DPHY Subsystem (Apr. 26, 2018)
  The newest member of the MIPI® PHY family, the C-PHY, arrived in October 2014 to a mixture of excitement and apprehension. How would this new C-PHY compare to the MIPI D-PHY and M-PHY®? What would differentiate the C-PHY, and would it be compatible enough with the D-PHY so that both could coexist in a hybrid subsystem? Now, years later, the answers are clear.
  
  
• Packet-based fronthaul - a critical enabler of 5G (Apr. 23, 2018)
  This paper will outline the benefits of a packet-based fronthaul technology to the business case for 5G NR virtualized RANs, and describe Comcores’ demonstrator. This provides detailed measurements based on four important enablers of the new RAN architecture - 5G NR; 100 MHz channels; IEEE 1914.3 RoE encapsulation and mapping; and functional splits which offload some of the baseband processing to the radio unit in order to boost fronthaul efficiency still further. There is also a coexistence path with installed CPRI links, and the eCPRI roadmap.