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IP / SOC Products Articles

• Types of Storages for Computing System-On-Chips (Mar. 05, 2018)
  We are living in an age where we generate the same amount of data each year that has been generated since antiquity. Ever wondered how and where these peta /exa/zetta bytes of data are stored?
  
  
• Three Design Aspects you shouldn't miss while building an NB-IoT Protocol Stack (Feb. 26, 2018)
  It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
  
  
• A design of High Efficiency Combo-Type Architecture of MIPI D-PHY and C-PHY (Feb. 05, 2018)
  MIPI C-PHY is suitable for mobile camera and display applications. In this paper, we proposed an effective active C-PHY driver scheme without any increase of the size and control pins. Additionally, C-PHY has many characteristics in-common with D-PHY because many parts of C-PHY were adapted from D-PHY. Therefore, we present a combo-type architecture of MIPI D-PHY and C-PHY.
  
  
• Types of Memories in Computing System-On-Chips (Jan. 29, 2018)
  What types of memories are needed for a computing system? Let me try to answer this question with an analogy. Have you ever solved a complex math problem without a paper?
  
  
• The Ideal Solution for AI Applications - Speedcore eFPGA (Jan. 22, 2018)
  Artificial intelligence (AI) is reshaping the way the world works, opening up countless opportunities in commercial and industrial systems. These new architectures will perform functions such as load balancing and allocating resources such as wireless channels and network ports based on predictions learned from experience.
  
  
• Run by Chips, Secured with Chips - Hardware Security with NeoPUF solutions (Jan. 08, 2018)
  eMemory NeoPUF Entropy IP provides a quality PUF entropy up to 64K bits, and NeoPUF Key Manager IP offers a ready-to-use key generator to accelerate time-to-market. The solutions address key issues of existing technologies and can secure the hardware from the very beginning of chip manufacture.
  
  
• A Brief History of Process Node Evolution (Jan. 02, 2018)
  The semiconductor industry has produced improved Integrated circuits (ICs) year after year by reducing chip area and making ICs more power efficient. In addition to new circuit innovations, a major driver for these improvements has been the advancement of fabrication process or technology nodes that essentially make electronic devices smaller and more power optimized.
  
  
• Understanding Flash memory (Dec. 18, 2017)
  Flash memory is currently the most widely used type of non-volatile memory. NAND Flash is optimised for file storage, to replace traditional disk drives. This article provides an overview of how NAND Flash technology works, and the role of the controller to optimise the performance and lifetime of the Flash memory.
  
  
• Modular Design Of Level-2 Cache For Flexible IP Configuration (Dec. 11, 2017)
  This paper presents an innovative level 2 cache design that meets the requirements of flexibility, configurability, low power, and small area for embedded systems.
  
  
• Dynamic Margining: The Minima Approach to Near-threshold Design (Nov. 30, 2017)
  Energy consumption has become the most important parameter for today’s batterypowered electronic devices. The need to reduce energy consumption has led the industry to reconsider the concept of near-threshold design. Legacy design, a static margining approach to power/performance trade-offs, will leave most of the potential energy savings on the table. New offerings in this arena include both integrated circuit (IC)-based and intellectual property (IP)-based solutions, where IP-based solutions offer a faster time-to-market among other benefits.
  
  
• IPs for automotive application - Functional Safety and Reliability (Nov. 27, 2017)
  An electronic design that can be used in multiple ASICs/SoCs is a potential “IP” in the semiconductor industry. The premise of semiconductor IP market is simple – IP vendor focuses on designing, maintaining and updating the IP and ASIC/SoC companies focus on their differentiation, thereby fuelling innovation and reducing time-to-market.
  
  
• The Secret to Building IP at the Cutting Edge (Nov. 20, 2017)
  At 7nm and beyond, the cost and time to develop IP is very high. To gain a suitable return, it's critical to have an efficient design methodology that produces a portfolio of attractive solutions in many process variants, metal stacks, Vt selections, and even completely different foundries.
  
  
• The Future of Microcontrollers (Nov. 20, 2017)
  Integration of eFPGA into microcontrollers is happening today now that this technology is available from multiple suppliers in 180nm to 16nm process nodes.
  
  
• Why is Analog increasingly important in the Digital Era? (Nov. 16, 2017)
  Since its invention in the `60s, integrated circuit development has seen an aggressive and cyclic pace for improvement pushed by specific disruptive applications. These once were military/aerospace, mainframe computer, minicomputer, personal computers, networking, mobile and more recently smartphones. The traditional approach has always been to make the most out of digital and support it, when needed, with analog submodules.
  
  
• Overcoming Timing Closure Issues in Wide Interface DDR, HBM and ONFI Subsystems (Nov. 13, 2017)
  In wide chip interfaces like DDR, HBM and ONFI, it can be challenging to synthesize and connect high-frequency controllers to the PHY hard macros. Clock trees can be expansive, pushing tools to their limits, and often multiple clock domains are needed.
  
  
• eFPGA IP Density, Portability & Scalability (Nov. 13, 2017)
  There are multiple eFPGA suppliers in the market today: Achronix, Adicsys, Efinix, Flex Logix™, Menta, QuickLogic. There are 3 different business models and engineering approaches to eFPGA which you should understand to assess how it will impact your success in using their eFPGA IP and their viability as a supplier long term.
  
  
• Rapid SoC Proof-Of-Concept For Zero Cost (Nov. 06, 2017)
  Your company provides analog/mixed-signal (AMS) and sensor-based ICs, but your best customer wants you to create a system on a chip (SoC) that includes a digital processor. With little experience with digital processors, you need to quickly provide a proof-of-concept to your customer that shows the viability of this new IC in the next few days. And, you have very little budget.
  
  
• The Battle of Data center Interconnect Fabric (Oct. 30, 2017)
  With the exponential increase in off-chip bandwidth requirement, chip-to-chip interconnect is turning out to be the bottleneck of the information highway. Such bottlenecks invariably drive a new wave of innovation. During 1990s and around the turn of the millennium, rapid adoption of personal computers and development of various IO devices fuelled early innovations in interconnect technology and interfaces such as SATA, SAS, USB, PCIe were defined.
  
  
• Combining USB Type-C and DisplayPort support in portable implementations (Oct. 09, 2017)
  Using USB Type-C connectors to combine both USB-C 3.1 and DisplayPort data streams, to support data, audio, video and power connections on a single port
  
  
• Power Management for Internet of Things (IoT) System on a Chip (SoC) Development (Sep. 18, 2017)
  There are many factors that must be considered when developing a custom System on a Chip (SoC) for Internet of Things (IoT) applications. Chief among these are the power management circuits on the die. Vidatronic offers this white paper to discuss these considerations and all of the various circuit blocks that can be found in this application. Vidatronic IP solutions are discussed and the benefits they bring to IoT SoC designers.
  
  
• Reduce Time to Market for FPGA-Based Communication and Datacenter Applications (Sep. 14, 2017)
  As FPGA-based realizations become bigger and more complex, synthesis tools that deliver an automated flow are the obvious choice for creating optimized designs in a timely manner.
  
  
• The case for integrating FPGA fabrics with CPU architectures (Aug. 28, 2017)
  Physics restricts how much further process geometry shrinkage can take us in terms of boosting processor throughput.
  
  
• Asynchronous reset synchronization and distribution - Special cases (Aug. 14, 2017)
  Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of asynchronous reset and explore advanced solutions for ASIC vs FPGA designs.
  
  
• Asynchronous reset synchronization and distribution - ASICs and FPGAs (Aug. 07, 2017)
  
  
  
• Asynchronous reset synchronization and distribution - challenges and solutions (Jul. 30, 2017)
  Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of asynchronous reset and explore advanced solutions for ASIC vs FPGA designs.
  
  
• Improving Battery-Powered Device Operation Time Thanks To Power Efficient Sleep Mode (Jul. 20, 2017)
  Allowing battery-powered devices to run, without battery recharge, for years rather than months, partakes in enhancing significantly end-user satisfaction and is a key point to enabling the emergence of IoT applications. Numerous applications, such as M2M, BLE, Zigbee…, have an activity rate (duty cycle) such that the power consumption in sleep mode dominates the overall current drawn by the SoC (System on Chip). For such applications, the design of the “Always-On power domain" (a.k.a AON power domain) is pivotal.
  
  
• Megatrends Drive 200mm Fab Renaissance (Jul. 17, 2017)
  The past year has seen a resurgent interest in 200mm fabrication. In this paper, I will discuss why this is and answer the question, "Can 200mm fabs have a profitable future?"
  
  
• Generating High Speed CSI2 Video by an FPGA (Jul. 17, 2017)
  In this article, we show how fast video streams conforming to MIPI CSI2 rev2.0 over MIPI DPHY rev1.2 can be generated, using VLSI Plus’ SVTPlus-CSI2-F IP core, with simple off-FPGA analog front-end. The high bit rates can be achieved with a relatively slow FPGA clock frequency, trading off FPGA resources for simple timing closure.
  
  
• How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs (Jul. 10, 2017)
  Here we provide rational for using Centar’s floating-point IP core for the new Altera Arria 10 and Stratix 10 FPGA platforms. After a short contextual discussion section, a comparison of various FFT designs follows based on compilations to a couple of FPGAs. Here it is shown that LUT/register usage can be drastically reduced with this new class of FPGAs. The following section summarizes why Centar’s architecture is so effective in taking advantage of the new DSP block hardware.
  
  
• Context Based Clock Gating Technique For Low Power Designs of IoT Applications - A DesignWare IP Case Study (Jul. 03, 2017)
  This paper discusses about the intelligent low power techniques such as context based clock gating and how they are useful for IoT applications. It also describes how it improves the overall power efficiency of the system. The power statistics shared shows how the overall idle power and functional power consumption is significantly reduced. Further we discuss about how it can be combined with few other low power techniques to reduce the overall power